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检索条件"任意字段=39th International Conference on Logic Programming"

共 519 条记录，以下是161-170 订阅

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A Compositional Semantics for Repairable BDMPs 39th

A Compositional Semantics for Repairable BDMPs

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39th international conference on Computer Safety, Reliability and Security (SAFECOMP)

作者： Khan, Shahid Katoen, Joost-Pieter Bouissou, Marc Rhein Westfal TH Aachen Software Modeling & Verificat Aachen Germany Elect France EDF R&D Palaiseau France

ISBN: (纸本)9783030545482;9783030545499

Boolean-logic Driven Markov Processes (BDMPs) is a graphical language for reliability analysis of dynamic repairable systems. Simulation and trace-based analysis tools for BDMPs exist and have been used to analyze reliability, safety and security aspects of industrially relevant case studies. To enable a model-based analysis of BDMPs, such as probabilistic model checking, formal semantics is indispensable. this paper presents a rigorous semantics to repairable BDMPs using Markov automata (MA), a variant of continuous-time Markov chains (CTMCs) with action transitions. the semantics is modular: an MA is associated with each BDMP element and these are combined to obtain an automaton for the entire BDMP. By ignoring the actions that are used to "glue" the MA of BDMP elements, a CTMC is obtained that is amenable to analysis by e.g., model checking. We report on a prototypical implementation and experimentally show that our semantics corresponds to the BDMP interpretation by the tool Yet Another Monte Carlo Simulation.

关键词： Reliability Dependability Formal methods Probabilistic model checking Monte-Carlo simulation Compositional analysis

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Efficient Translation of Safety LTL to DFA Using Symbolic Automata Learning and Inductive Inference 39th

Efficient Translation of Safety LTL to DFA Using Symbolic Au...

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39th international conference on Computer Safety, Reliability and Security (SAFECOMP)

作者： Giantamidis, Georgios Basagiannis, Stylianos Tripakis, Stavros United Technol Res Ctr Ireland Cork Ireland Aalto Univ Otaniemi Finland Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9783030545482;9783030545499

Safety LTL properties are ubiquitous in the verification of safety critical systems. there is already evidence that translating safety properties into DFA rather than Buchi automata results in faster verification times. Conventional translation strategies can in some cases use unnecessarily large amounts of resources. We develop a symbolic adaptation of the L* active learning algorithm tailored to efficiently translate safety LTL properties into symbolic DFA. We demonstrate how an inductive inference procedure can be used to provide additional input to the algorithm that greatly improves performance for certain important families of properties. For completeness, we also provide an outline and examples of how such a procedure can be implemented. Finally, we compare with state of the art LTL translators and provide experimental evidence where our approach significantly outperforms conventional translation strategies.

关键词： Linear Temporal logic Safety properties Automata learning Symbolic automata Inductive inference

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Ranking-based Placement of IC logic Cells 39

Ranking-based Placement of IC Logic Cells

引用

39th IEEE international conference on Electronics and Nanotechnology (ELNANO)

作者： Melikyan, V. Sh. Harutyunyan, A. G. Martirosyan, A. R. Synopsys Armenia CJSC Yerevan Armenia Natl Polytech Univ Armenia Yerevan Armenia

ISBN: (纸本)9781728120652

A method for placing logic cells of integrated circuits (IC) that takes into account the functional and logical features of the circuit. the proposed method is based on taking into account the flow of signals in the logic circuit. According to the proposed approach, a preliminary ranking of logical cells is performed, the results of which are later used in their placement. In accordance with the proposed method, an algorithm and software tool for allocation of logic ICs have been developed. Testing the program on test circuits showed the effectiveness of the proposed method.

关键词： digital integrated circuit logical cell placement signal flow graph element ranking

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Nano-Processor for the Small Tasks 39

Nano-Processor for the Small Tasks

引用

39th IEEE international conference on Electronics and Nanotechnology (ELNANO)

作者： Sergiyenko, Anatoliy Molchanov, Oleksii Orlova, Maria Igor Sikorsky Kyiv Polytech Inst Dept Comp Engn Kiev Ukraine Igor Sikorsky Kyiv Polytech Inst Dept Syst Programming & Specialized Comp Syst Kiev Ukraine

ISBN: (纸本)9781728120652

the eight-bit stack processor architecture is proposed, which is designed for the FPGA implementation. the microprocessor with this architecture has small hardware costs, reduced software amount, and ability to add up to hundred new user instructions to its instruction set. the microprocessor architecture is adapted for programming the serial port communications and is able to perform the data stream parsing. It is effectively used for the Internet of things applications.

关键词： stack processor Forth FPGA VHDL IoT

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Semi-distributed Contention-based Resource Allocation for Ultra Reliable Low Latency Communications 38

Semi-distributed Contention-based Resource Allocation for Ul...

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39th IEEE international conference on Computer Communications (IEEE INFOCOM)

作者： Brown, Patrick Elayoubi, Salah Eddine Orange Labs 905 Rue Albert Einstein F-06560 Valbonne France Univ Paris Saclay L2S UMR CNRS 8506 Cent Supelec 3 Rue Joliot Curie F-91190 Gif Sur Yvette France

ISBN: (纸本)9781728164120

Many Industrial Internet of things (IIoT) use cases are characterized by a large number of users transmitting sporadically packets to a central controller. the transmitted packets have to be conveyed within a very short time so that it is not possible to make per-packet resource reservation, and contention-based access is needed, which is conflicting with the very stringent reliability constraints. In order to achieve both reliability and latency constraints, we consider in this paper the combination of contention-based access with blind replication of packets. Knowing the limited, but large, number of potential users in the system, we propose a semi-centralized channel access scheme where each user is pre-allocated positions for its replicas in case he has a packet to convey. We show, using coding theory, how to design sequences for users so that the number of collisions is minimized. We further exploit our pre-allocation scheme to develop a successive interference cancellation method where the base station tries to decode a packet based on the knowledge of the already decoded colliding packet. We show that the proposed schemes succeed to attain very low loss rates with low resource reservation.

关键词： Computer programming

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SuSy: A programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs 20

SuSy: A Programming Model for Productive Construction of Hig...

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39th IEEE/ACM international conference On Computer Aided Design (ICCAD)

作者： Lai, Yi-Hsiang Rong, Hongbo Zheng, Size Zhang, Weihao Cui, Xiuping Jia, Yunshan Wang, Jie Sullivan, Brendan Zhang, Zhiru Liang, Yun Zhang, Youhui Cong, Jason George, Nithin Alvarez, Jose Hughes, Christopher Dubey, Pradeep Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA Intel San Jose CA USA Peking Univ Beijing Peoples R China Tsinghua Univ Beijing Peoples R China Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)9781665423243

Systolic algorithms are one of the killer applications on spatial architectures such as FPGAs and CGRAs. However, it requires a tremendous amount of human effort to design and implement a high-performance systolic array for a given algorithm using the traditional RTL-based methodology. On the other hand, existing high-level synthesis (HLS) tools either (1) force the programmers to do "micro-coding" where too many optimizations must be carried out through tedious code restructuring and insertion of vendor-specific pragmas, or (2) give them too little control to influence a push-button compilation flow to achieve high quality of results. To tackle these challenges, we introduce SuSy, a programming framework composed of a domain-specific language (DSL) and a compilation flow that enables programmers to productively build high-performance systolic arrays on FPGAs. With SuSy, programmers express the design functionality in the form of uniform recurrence equations (UREs), which can describe algorithms from a wide spectrum of applications as long as the underlying computation has a uniform dependence structure. the URE description in SuSy is followed by a set of decoupled spatial mapping primitives that specify how to map the equations to a spatial architecture. More concretely, programmers can apply space-time transformations and several other memory and I/O optimizations to build a highly efficient systolic architecture productively. Experimental results show that SuSy can describe various algorithms with UREs and generate high-performance systolic arrays by spatial optimizations. For instance, the SGEMM benchmark written in SuSy can approach the performance of the manual design optimized by experts, while using 30x fewer lines of code.

关键词： DSL FPGA Systolic Array Space-Time Transformation URE

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the Importance of Being thing Or the Trivial Role of Powering Serious IoT Scenarios 39

The Importance of Being Thing Or the Trivial Role of Powerin...

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39th IEEE international conference on Distributed Computing Systems (ICDCS)

作者： Helal, Sumi Khaled, Ahmed Lindquist, Wyatt Univ Lancaster Sch Comp & Comm InfoLab21 Lancaster LA1 4WA England NE Illinois Univ Comp Sci Dept Chicago IL 60625 USA

ISBN: (纸本)9781728125190

In this article, we call for a "Walk Before You Run" adjustment in the Internet-of-things (IoT) research and development exercise. Without first settling the quest for what thing is or could be or do, we run the risk of presumptuous visions, or hypes, that can only fail the realities and limits of what is actually possible, leading to customers and consumers confusion as well as market hesitations. Specifically, without a carefully-designed thing architecture in place, it will be very difficult to find the "magic" we are so addicted and accustomed to programming! programming the IoT, as we once programmed the mainframe, the workstation, the PC and the mobile devices, is the natural way to realize a fancy IoT scenario or an application. Without thing architectures and their enablement of new programming models for IoT we will continue to only envision fancy scenarios but unable to unleash the IoT full potential. this article raises these concerns and provides a view into the future by first looking back into our short history of pervasive computing. the article focuses on the domain of "Personal" IoT and will address key new requirements for such thing architecture. Also, practicing what we preach, we present our ongoing efforts on the Atlas thing Architecture showing how it supports a variety of thing notions, and how it enables novel models for programmability.

关键词： Internet of things thing Architectures Pervasive Computing IoT programming Models Mobile Apps as IoT things

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OSTIA: A Low Cost Alternative for Short Summative Assessments in Massive programming Courses

OSTIA: A Low Cost Alternative for Short Summative Assessment...

引用

Computer Science Society (SCCC) international conference Chilean FLAGGED

作者： Juan Salas-Morales Jorge Munoz-Gama Escuela de Ingeniería Pontificia Universidad Católica de Chile Santiago Chile

the following topics are dealt with: computer aided instruction; educational courses; educational institutions; teaching; computer science education; Internet; further education; learning (artificial intelligence); en... 详细信息

ISBN: (数字)9781728183282

ISBN: (纸本)9781728183299

关键词： Computers Plagiarism Operating systems programming Mobile applications

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Partitioning Attacks on Bitcoin: Colliding Space, Time, and logic 39

Partitioning Attacks on Bitcoin: Colliding Space, Time, and ...

引用

39th IEEE international conference on Distributed Computing Systems (ICDCS)

作者： Saad, Muhammad Cook, Victor Lan Nguyen thai, My T. Mohaisen, Aziz Univ Cent Florida Orlando FL 32816 USA Univ Florida Gainesville FL 32611 USA

ISBN: (纸本)9781728125190

Bitcoin is the leading example of a blockchain application that facilitates peer-to-peer transactions without the need for a trusted third party. this paper considers possible attacks related to the decentralized network architecture of Bitcoin. We perform a data driven study of Bitcoin and present possible attacks based on spatial and temporal characteristics of its network. Towards that, we revisit the prior work, dedicated to the study of centralization of Bitcoin nodes over the Internet, through a fine-grained analysis of network distribution, and highlight the increasing centralization of the Bitcoin network over time. As a result, we show that Bitcoin is vulnerable to spatial, temporal, spatio-temporal, and logical partitioning attacks with an increased attack feasibility due to the network dynamics. We verify our observations by simulating attack scenarios and the implications of each attack on the Bitcoin network. We conclude with suggested countermeasures.

关键词： Bitcoin Peer-to-peer computing Blockchain Organizations IP networks Software Internet

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Predictive Scheduling for Virtual Reality 38

Predictive Scheduling for Virtual Reality

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39th IEEE international conference on Computer Communications (IEEE INFOCOM)

作者： Hou, I-Hong Naghsh, Narges Zarnaghi Paul, Sibendu Hu, Y. Charlie Eryilmaz, Atilla Texas A&M Univ Dept ECE College Stn TX 77840 USA Purdue Univ Sch ECE W Lafayette IN 47907 USA Ohio State Univ Dept ECE Columbus OH 43210 USA

ISBN: (数字)9781728164120

ISBN: (纸本)9781728164120

A significant challenge for future virtual reality (VR) applications is to deliver high quality-of-experience, both in terms of video quality and responsiveness, over wireless networks with limited bandwidth. this paper proposes to address this challenge by leveraging the predictability of user movements in the virtual world. We consider a wire-less system where an access point (AP) serves multiple VR users. We show that the VR application process consists of two distinctive phases, whereby during the first (proactive scheduling) phase the controller has uncertain predictions of the demand that will arrive at the second (deadline scheduling) phase. We then develop a predictive scheduling policy for the AP that jointly optimizes the scheduling decisions in both phases. In addition to our theoretical study, we demonstrate the usefulness of our policy by building a prototype system. We show that our policy can be implemented under Furion, a Unity-based VR gaming software, with minor modifications. Experimental results clearly show visible difference between our policy and the default one. We also conduct extensive simulation studies, which show that our policy not only out-performs others, but also maintains excellent performance even when the prediction of future user movements is not accurate.

关键词： Quality of experience Scheduling Wireless communication Headphones Optimal scheduling Linear programming

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