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检索条件"任意字段=3rd Aegean Workshop on Computing: VLSI Algorithms and Architectures, AWOC 1988"

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

ISBN: (纸本)9780387968186

The proceedings contain 46 papers. The special focus in this conference is on computing: vlsi algorithms and architectures. The topics include: Optimal parallel evaluation of tree-structured computations by raking (extended abstract);on finding lowest common ancestors: Simplification and parallelization: Extended summary;A scheduling problem arising from loop parallelization on MIMD machines;scheduling dags to minimize time and communication;computing a perfect matching in a line graph;separation pair detection;graph embeddings 1988: Recent breakthroughs, new directions;simulating binary trees on hypercubes;embedding rectangular grids into square grids;fast parallel and sequential algorithms for edge-coloring planar graphs: extended abstract;Efficient reconfiguration of vlsi arrays: Extended abstract;embedding grids into hypercubes;compaction on the torus: Extended abstract;channel routing with short wires;simple three-layer channel routing algorithms;applying the classification theorem for finite simple groups to minimize pin count in uniform permutation architectures: Extended abstract;a new algorithm for wiring layouts;Input sensitive vlsi layouts for graphs of arbitrary degree;Fast self-reduction algorithms for combinatorial problems of vlsi design;Regular structures and testing: RCC-adders: Extended abstract;optimal parallel algorithms on planar graphs;Parallel simulation and test of vlsi array logic;Universal hashing in vlsi;converting affine recurrence equations to quasi-uniform recurrence equations;better computing on the anonymous ring: Extended Abstract;Network complexity of sorting and graph problems and simulating CRCW PRAMS by interconnection networks: Preliminary version;analysis of a distributed scheduler for communication networks;weighted distributed match-making: Preliminary version;a tradeoff between information and communication in broadcast protocols;families of consensus algorithms.

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vlsi algorithms and architectures: 3rd aegean workshop on computing, awoc 88 Corfu, Greece, June 28 – July 1, 1988 Proceedings 1

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丛书名： Lecture Notes in Computer Science 319

1988年

作者： Mikhail J. Atallah Michael T. Goodrich (auth.) John H. Reif (eds.)

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Better computing on the anonymous ring: Extended Abstract 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Attiya, Hagit Snir, Marc Dept. of Computer Science Tel-Aviv University Tel-Aviv69978 Israel IBM T. J. Watson Research Center Yorktown HeightsNY10598 United States

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computing a perfect matching in a line graph 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Naor, Joseph Department of Computer Science University of Southern California Los AngelesCA90089-0782 United States

ISBN: (纸本)9780387968186

We show in this paper that a perfect matching of a line graph can be computed in NC. A necessary and sufficient condition for a line graph to have a perfect matching is an even number of vertices. To compute the perfect matching, we use a technique of dividing the graph into kingdoms. This result is equivalent to partitioning the edge set of a graph into edge disjoint paths of even length. © 1988, Springer-Verlag.

关键词： Graph theory

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Efficient reconfiguration of vlsi arrays: Extended abstract 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Codenotti, Bruno Tamassia, Roberto Istituto di Elaborazione dell'Informazione Consiglio Nazionale delle Ricerche Pisa56100 Italy Coordinated Science Laboratory University of Illinois at Urbana-Champaign UrbanaIL61801 United States

ISBN: (纸本)9780387968186

We consider the problem of reconfiguring a 2-dimensional vlsi array with faulty cells. A network flow model of the problem is formulated and an algorithm is presented for interconnecting the functional cells of the array so that they simulate a fault-free array of smaller size. Experimental results on the practical performance of this algorithm and of other techniques previously proposed in the literature are reported. © 1988, Springer-Verlag.

关键词： vlsi circuits

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Universal hashing in vlsi 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Fürer, Martin Computer Science Department The Pennsylvania State University 113 Whitmore Lab. University ParkPA16802 United States

ISBN: (纸本)9780387968186

A problem is presented with deterministic vlsi complexity ATdet2=Ω(N2), but Las Vegas complexity only ATLas Vegas2=O (N poly(logN)). (The Las Vegas algorithm always decides correctly, but T is only the expected running time;A is the area of the chip). Previously ATLas Vegas2=O(N3/2 poly(logN)) has been shown for a similar problem with a more complicated algorithm. Here, we use a simple universal hashing technique based on random linear functions. We hope this will give rise to other applications of universal hashing in vlsi. Our algorithm is very practical, because the random bits can even be wired into the chip. For every sequence of inputs during a chip's lifetime, the chances are high that the same short random bit string will always produce the result quickly. © 1988, Springer-Verlag.

关键词： vlsi circuits

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Fast self-reduction algorithms for combinatorial problems of vlsi design 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Fellows, Michael R. Langston, Michael A. Department of Computer Science University of Idaho MoscowID83843 United States Department of Computer Science Washington State University PullmanWA99164-1210 United States

ISBN: (纸本)9780387968186

In a recent series of papers [FL1, FL2, FL3], we have proven the existence of decision algorithms with low-degree polynomial running times for a number of well-studied vlsi layout, placement and routing problems. These results make use of the powerful Robertson-Seymour theorems on the well-partial-ordering of graphs under both the minor and immersion orders. In the present paper, we study the complexity of construction versions of these problems, focusing on efficient self-reduction strategies. We introduce a notion of fast self-reduction in this setting and develop a general technique, which we term scaffolding, that is useful in the design of fast self-reduction algorithms. © 1988, Springer-Verlag.

关键词： Integrated circuit design

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Input sensitive vlsi layouts for graphs of arbitrary degree 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Sherlekar, Deepak D. Jájá, Joseph University of Michigan United States University of Maryland United States

ISBN: (纸本)9780387968186

A general method to find area-efficient vlsi layouts of graphs of arbitrary degree is presented. For graphs of maximum degree Δ, the layouts obtained are smaller by a factor of Δ2 than those obtained using existing methods. Optimal planar layouts, and near-optimal nonplanar layouts are also derived for planar graphs of arbitrary degree and gauge. The results span the spectrum between outerplanar graphs (gauge 1), and arbitrary planar graphs (gauge O(n)). Optimality is established by developing families of planar graphs of varying gauge and degree, and proving lower bounds on their layout area. These techniques can be combined to exhibit a trade-off between area and the number of contact cuts. The resulting scheme is sensitive to all three parameters that affect the area: the maximum degree, the gauge, and the number of contact cuts. © 1988, Springer-Verlag.

关键词： Gages

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Parallel simulation and test of vlsi array logic 3rd

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3rd aegean workshop on computing: vlsi algorithms and architectures, awoc 1988

作者： Bose, Pradip IBM T. J. Watson Research Center H2-B48 P. O. Box 704 Yorktown HeightsNY10598 United States

ISBN: (纸本)9780387968186

We consider the task of accelerating existing array logic CAD software by running them under parallel processing environments. We restrict our discussion to vlsi programmable logic arrays (PLAs);we present results based on fault simulation/test generation software implemented for PLAs. Due to the regular layout of such array logic, considerable parallelism is expected in any data processing problem involving these modules. However, depending on the underlying machine model, and the adopted programming model, varying levels of speed-up are exhibited. We first consider a typical pipelined, vector mainframe like the IBM 3090 VF. Through a combination of novel problem reformulation strategies, and educated coding guidelines for vector machines, we show how an original scalar program can be efficiently speeded up on such machines. The other machine model considered is that of a shared memory parallel processing system. Our results here are based on experiments run under an experimental multi-processor VM environment (VM/EPEX) which has been set up to predict the possible speed-up on a parallel processor such as RP3. The overall processing environment is assumed to be constrained to a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically-intensive applications. © 1988, Springer-Verlag.

关键词： Parallel processing systems

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