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检索条件"任意字段=3rd IEEE International Conference on Reconfigurable Computing and FPGAs"

共 389 条记录，以下是1-10 订阅

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Towards Resource Efficient and Low Latency CNN Accelerator for fpgas: Review and Evaluation 3

Towards Resource Efficient and Low Latency CNN Accelerator f...

引用

3rd international conference on Embedded Systems and Artificial Intelligence, ESAI 2024

作者： Amin, Rashed Al Obermaisser, Roman Institute for Embedded Systems University of Siegen Siegen Germany

ISBN: (纸本)9798331522056

Convolutional Neural Networks (CNNs) have seen widespread adoption in various domains, including speech recognition, image classification, and segmentation. However, their computational demands necessitate dedicated and reconfigurable hardware architectures, such as FieldProgrammable Gate Arrays (fpgas). Despite the numerous advantages of CNN accelerators including enhanced efficiency within diverse application contexts, their deployment on fpgas must address challenges related to energy consumption, computational demands, and resource optimization. Both academia and industries are actively engaged in research and development aimed at designing resource-efficient and lowlatency CNN accelerators for fpgas. However, there has been relatively little attention paid to the dynamic comprehensive analysis and evaluation in which CNN accelerators equipped with fpgas operate. This paper aims to bridge this gap by conducting a comprehensive survey and evaluation of CNN accelerator techniques for fpgas, focusing on resource utilization, latency, and power consumption. This study investigates the performance of CNN accelerators for fpgas, considering a range of hardware architectures and optimization techniques, from multiplier designs to complex heterogeneous pipelining. Furthermore, the paper highlights the challenges faced by FPGA-based CNN accelerators, particularly the tradeoffs between resource utilization and latency, based on the characteristics of the data and devices involved. The insights gleaned from this review can offer valuable guidance and inspiration to researchers, engineers, and students working in these domains, facilitating further advancements in FPGAbased CNN accelerator technology. © 2024 ieee.

关键词： reconfigurable architectures

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The Deep Neural Network Compilers for fpgas: A Survey 3

The Deep Neural Network Compilers for FPGAs: A Survey

引用

3rd international conference on Electronic Information Engineering and Computer Communication, EIECC 2023

作者： Tian, Jing Shi, Tianjie Zhao, Yixuan Liu, Feiyang Xi'An Aeronautics Computing Technique Research Institute AVIC Xi'an China

ISBN: (纸本)9798350359961

In embedded systems, the low-latency, low-power consumption, and reconfigurable FPGA component undertakes the inference operations of a large number of computationally intensive tasks, such as artificial intelligence algorithms, making the deep neural network compiler for fpgas a hot topic. This FPGA compiler can automatically optimize the model calculation diagrams and hardware structure design, and can achieve the end-To-end deployment of neural network models, efficiently and rapidly. This paper summarizes the general framework structure of the neural network compiler for fpgas, focuses on the development of three representative compilers, compares the deployment performance of specific algorithms on the FPGA platform, summarizes the development advantages and limitations, and finally proposes its application prospects and important research directions in embedded systems, providing a theoretical basis for the rapid iteration and deployment of artificial intelligence algorithms in embedded computing systems. © 2023 ieee.

关键词： algorithm deployment artificial intelligence algorithms compilers deep neural network FPGA

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Examining Floating Point Precision in Contemporary fpgas 3

Examining Floating Point Precision in Contemporary FPGAs

引用

3rd international conference on Electrical, Electronics, Information and Communication Technologies, ICEEICT 2024

作者： Mythile, C. Jaisiva, S. Arunadevi, A. Sudhapriya, K. Sri Krishna College of Technology Department of Eee Tamil Nadu Coimbatore India Nehru Institute of Engineering and Technology Department of Mechatronics Tamil Nadu Coimbatore India

ISBN: (数字)9798350369083

ISBN: (纸本)9798350369083

Current computer systems use an approximation of real numbers to perform calculations, which are frequently based on a particular FP (Floating-Point) format. The bit width of the relevant Fraction (F), and Exponent (E) fields determines the enhanced dynamic range and precision of FP numbers in comparison to a fixed number of points. Usually, point of floating precisions have been made available by designs like central processing units (CPUs) and Unit for Processing Graphics. These precisions were primarily bit of 16, bit of 32 and bit of 64 widths also referred to as half and single along format with double-precision. On the other hand, reconfigurable architectures, like fpgas (Field Programmable Gate Arrays), enable creators to achieve the optimal harmony of precision, dynamic range, energy efficiency, and rapidity by enabling the implementation of nearly any required custom precision to suit certain workload types. For custom-precision floating precision, this effort suggests a recursive Chisel-based generator that can execute common yet fundamental operations including sum of two, abate of two, multiple of two, and accumulation of multiple. Specifically, it present a comprehensive preliminary investigation that illustrates the expect results on several type and generation of fpgas, covers all elements of field of area, power, and speed. © 2024 ieee.

关键词： reconfigurable architectures

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Optimizing RGB to Grayscale, Gaussian Blur and Sobel-Filter operations on fpgas for reduced dynamic power consumption 3

Optimizing RGB to Grayscale, Gaussian Blur and Sobel-Filter ...

引用

3rd international conference on Artificial Intelligence For Internet of Things, AIIoT 2024

作者： Rout, Nikhil Jean Jenifer Nesam, J. Chennai Campus Chennai India

ISBN: (纸本)9798350372120

The conversion of pixels from their RGB to Grayscale formats is a crucial first step in numerous Image Pre-Processing, Computer Vision, and as highlighted here, edge detection modules. This paper presents an implementation of the Shift-Add Multiplication algorithm for efficient constant multiplications of the NTSC formula weights for RGB to Grayscale conversion on fpgas. The proposed module is designed to be reconfigurable to both fixed-point and floating-point formats, providing flexibility in precision and resource utilization based on application requirements. Additionally, a Python script was developed to automate the generation of Verilog code for fractional constant multiplications, as proposed in this study. Pipelined modules for Gaussian Blur and the Sobel-Filter were also designed to enable the development of a complete real-time edge detection system on fpgas. The findings reveal that Shift-Add algorithm based multiplier's significantly reduce dynamic power consumption as compared to the use of the built-in DSP blocks on FPGA boards while performing constant multiplications for RGB to Grayscale conversion. © 2024 ieee.

关键词： Field programmable gate arrays (FPGA)

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Integer-Based Homomorphic Encryption: Evaluation and FPGA Performance Enhancements 3

Integer-Based Homomorphic Encryption: Evaluation and FPGA Pe...

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3rd international conference on Communication, Control, and Intelligent Systems, CCIS 2024

作者： Singh, Gurdeep Mittal, Sonam Chitkara University Institute of Engineering and Technology Chitkara University Punjab India

ISBN: (纸本)9798331528201

In this paper, we provide a thorough literature review on the field of integer homomorphic encryption when it is incorporated into fpgas. Homomorphic encryption allows one to perform operations on ciphertexts and get results, that, when decrypted, match the outcome of operations performed on the plaintexts. First, different integer-based homomorphic encryption schemes are investigated, namely their efficiencies in implementation, their security, and compatibility with FPGA architecture. Finally, a comparative analysis table is presented that indicates some important parameters such as the encryption and decryption rates, resources needed, and the adaptability of each scheme. This survey is therefore intended to help researchers and practitioners make correct decisions on the integer homomorphic encryption designs that are suitable for their respective FPGA applications, given the increasing demand for secure data processing services in cloud computing and other environments where sensitive data is handled. © 2024 ieee.

关键词： Computational efficiency Cryptographic hardware implementations Ethnicity Field Programmable Gate Arrays (fpgas) Hardware acceleration Homomorphic Encryption (HE) Integer-based Privacy-preserving computation Secure data processing Sustainable

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Hilbert curve based optically interfaced microwave resonator for reconfigurable wireless systems 3

Hilbert curve based optically interfaced microwave resonator...

引用

3rd international conference on Intelligent and Innovative Technologies in computing, Electrical and Electronics, IITCEE 2025

作者： Santhanam, Suganthi Palavesam, Thiruvalar Selvan K.Ramakrishnan College of Technology Department of Electronics and Communication Engineering Tamilnadu Tiruchirappalli India Srm Trp Engineering College Department of Electronics and Communication Engineering Tamilnadu Tiruchirappalli India

ISBN: (纸本)9798331515911

The proposed design uses the 2×2 integration architecture as an array that is recovered to a T-resonator in order to access the Hilbert curve. In conjunction with a transmission line that has two air gaps, the resulting combination reaches a resonance frequency of around 0.8 GHz. The proposed deive is mounted on a 1.6 mm FR4 substrate that is 50 × 50 mm. CST technique improves the obtained plan dimensions. Based on numerical calculations, the functioning of the suggested resonator is assessed using the S11 and S21 parameters. Two varactor diodes circuits are included for reconfiguration in order to regulate the frequency range as well as the parameters associated with the relevant frequency band. © 2025 ieee.

关键词： Varactors

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A Novel reconfigurable Intelligent Surfaces-Assisted Communication-Positioning Strategy 3

A Novel Reconfigurable Intelligent Surfaces-Assisted Communi...

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3rd international conference on computing, Communication, Perception and Quantum Technology, CCPQT 2024

作者： Zheng, Xiaofan Guo, Jianyan Tian, Yue School of Opto-electronic and Communication Engineering Xiamen University of Technology Xiamen China

ISBN: (纸本)9798331528386

As an emerging electromagnetic metamaterial with revolutionary potential, reconfigurable intelligent surfaces (RIS) can enhance long-distance communication, reduce the impact of obstacles between the user equipment (UE) and base station (BS), and realize the localization of the UE through intelligent manipulation of radio waves. This paper proposes a collaborative localization and communication combined strategy based on received signal strength indication (RSSI). Under the premise of imperfect channel state information (CSI), this strategy establishes the terminal positioning model of a RIS-assisted wireless communication system based on weak barriers by utilizing the function of RIS flexible configuration of reflection parameters. Compared with the traditional trilateration and triangulation, the proposed Communication-Positioning (CP) based RIS-assisted strategy greatly improves the utilization rate of the BSs. © 2024 ieee.

关键词： Channel state information

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A CPW Fed Hexagonal Patch Frequency reconfigurable Antenna for Multiple Applications 3

A CPW Fed Hexagonal Patch Frequency Reconfigurable Antenna f...

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3rd international conference on Advances in Electrical, computing, Communication and Sustainable Technologies, ICAECT 2023

作者： Suman, Prem Nath Mishra, Gajendra Kant Birla Institute of Technology Mesra Electronics and Communication Engineering Ranchi India

ISBN: (纸本)9781665494007

This manuscript incorporates a coplanar waveguide fed a simple low-profile antenna to achieve frequency reconfigurability. The proposed structure in the PIN diode is attached in between the hexagonal patch and the rectangular slot. The Proposed frequency reconfigurable antenna structure provided frequency variations as the PIN Diode is switched. The resonating frequencies are 5.61 GHz, 9.59 GHz as PIN Diode is on, 6.74 GHz, 11.20 GHz, and 14.83 GHz as the PIN diode is off, providing maximum gain up to 7.73 dBi. This multiple-frequency variation of the antenna enables the antenna to use for multiple applications. © 2023 ieee.

关键词： Coplanar waveguides

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Air-Ground Physical Layer Security Transmission Scheme Assisted by reconfigurable Intelligent Surfaces 3

Air-Ground Physical Layer Security Transmission Scheme Assis...

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3rd international conference on computing, Communication, Perception and Quantum Technology, CCPQT 2024

作者： Li, Kaixuan Zhao, Xiao Yu, Kan Yuan, Wenli Liu, Xiaowu Feng, Zhiyong Li, Dong School of Computer Science Qufu Normal University Rizhao China School of Computer Science and Engineering Macau University of Science and Technology Taipa China Key Laboratory of Wave Scattering and Remote Sensing Information Beijing University of Posts and Telecommunications Beijing China

ISBN: (纸本)9798331528386

Unmanned aerial vehicles (UAVs) play a crucial role in wireless communication networks due to their mobility, line-of-sight (LoS) link, flexible, and on-demand deployment advantages. To address the challenge of secure air-to-ground transmission, this paper investigates a communication model where UAV is equipped with reconfigurable intelligent surfaces (RIS) to serve as relay. Specifically, the beamforming (BF), RIS phase shift and UAV flight trajectory are jointly optimized to maximize the average secrecy rate (ASR). Then, the non-convex problem is decomposed into three sub-problems and addressed using alternating optimization (AO) algorithm. The results of the simulations serve to confirm the efficacy of the proposal regarding the PLS scheme. © 2024 ieee.

关键词： Unmanned aerial vehicles (UAV)

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Acceleration of FFT Algorithm Based on reconfigurable computing Architecture 3

Acceleration of FFT Algorithm Based on Reconfigurable Comput...

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3rd ieee international conference on Intelligent Technology and Embedded Systems, ICITES 2023

作者： Li, Ting Wang, Hanning Peng, Guiqiang Liu, Leibo Xie, Tuo Liu, Mingxu Wei, Shaojun School of Integrated Circuits Tsinghua University Beijing China Beijing Superstring Academy of Memory Technology Beijing China

ISBN: (纸本)9798350343755

Embedded applications have high requirements for computing speed, power consumption, and cost. Traditional computing models cannot meet the emerging application scenarios and requirements. In computing-intensive fields, fast Fourier transform (FFT) is a key technical means, but the implementation of this algorithm requires complex computation and required to be accelerated urgently. To solve the above problems, this paper proposed a FFT hardware acceleration method based on the coarse-grained reconfigurable array (CGRA). By mapping the FFT core operations to hardware units, the calculation speed can be significantly increased. Experimental results show that the proposed FFT acceleration method is more efficient than related implementations. © 2023 ieee.

关键词： Fast Fourier transforms

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