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检索条件"任意字段=3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology"

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VLSI Floorplanning Based on Particle Swarm Optimization

VLSI Floorplanning Based on Particle Swarm Optimization

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3rd International Conference on Intelligent System and Knowledge engineering

作者： Chen, Guolong Guo, Wenzhong Cheng, Hongju Fen, Xiang Fang, Xiaotong Fuzhou Univ Coll Math & Comp Sci Fuzhou 350002 Peoples R China

ISBN: (纸本)9781424421961

Floorplanning is an important problem in the very large integrated circuit (VLSI) design automation. It's an NP-hard combinatorial optimization problem. The Particle Swarm Optimization (PSO) has been proved to be a good optimization algorithm. with outstanding global performance. However, PSO cannot be directly used in the combinatorial optimization problem due to its continuous characterisic. In this paper a novel floorplanning algorithm based on Discrete PSO (DPSO) algorithm is proposed, in which integer coding based on module number was adopted The principles of mutation and crossover operator in the Genetic Algorithm (GA) are also incorporated into the proposed PSO algorithm to achieve better diversity and break away from local optima. Experiments employing MCN and GSRC benchmarks show that the performance of our proposed algorithm for placement is good. The proposed algorithm can avoid the solution from falling into local minimum and have good convergence performance.

关键词： Very large scale integration Particle swarm optimization Intelligent systems Knowledge engineering Mathematics Space technology Educational institutions Computer science Laboratories application software

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Development and application of reliability analysis system for medium and high voltage distribution networks

Development and application of reliability analysis system f...

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3rd International Conference on Deregulation and Restructuring and Power Technologies, DRPT 2008

作者： Hongyun, Zhang Pengxiang, Bi Xiaojun, Zhong Qing, Jin Shaanxi Electric Power Company Xi'an 710048 China Department of Electrical Engineering Northwest Electric Power Staff College Xi'an 710054 China

ISBN: (纸本)9787900714138

In order to identify the bottleneck weaknesses of a distribution network so as to improve service reliability of the network by effective upgrading, we developed the power flow calculation based reliability analysis software for high-voltage distribution networks and the fault pervasion algorithm based reliability analysis system for medium-voltage distribution networks. Taking into account multiple factors, including line failure rate, repair time, isolation operation time and switching operation time, the system software can calculate the reliability indices and static security indices of node, feeder and system, and analyze the effect of reliability parameter variation, the influence of component reliability, the sensitivity to component reliability, and the bottleneck weaknesses of distribution networks. Actual application of the systems in calculation and analysis of power flow and reliability of Xi'an and other three regional medium and high voltage distribution networks manifested the bottleneck weaknesses of the networks, and found out various existing problems in reliability management. After effective measures are taken, good social and economic benefits were achieved. © 2008 DRPT.

关键词： Reliability analysis

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Transparent connectivity for embedded system design

Transparent connectivity for embedded system design

引用

3rd International Multi-Conference on Computing in the Global Information technology, ICCGI 2008

作者： Pearson, C. Giuma, T. Harris, A. Scribner Associates Southern Pines NC 28387 United States University of North Florida Jacksonville FL 32224 United States

ISBN: (纸本)9780769532752

Embedded system design is a topic of interest to multidisciplinary fields including electrical engineering and computer science. In order to correctly focus on the correct aspects of embedded system design, be it hardware for electrical engineering students, or software for computer science students, seamless connectivity between the hardware and software aspects needs to be provided. One approach to provide students from both fields with practical experience is to develop a transparent bridge between the hardware and software layers of the embedded system design. In this paper we demonstrate a Universal Serial Bus/Serial Peripheral Interface (USB/SPI) transparent bridge to interface an embedded system to a personal computer. The bridge consists of a hardware module that transmits the embedded system data through SPI to a PC using USB. A device driver for the USB/SPI Bridge provides a straightforward application programming interface to the embedded system. The bridge can aide students studying embedded system design and students studying computer software development to collaborate on design projects. © 2008 ieee.

关键词： Embedded systems

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SIGSAND-EUROPE 2008: Proceedings of the 3rd AIS SIGSAND European symposium on Analysis, Design, Use and Societal Impact of Information systems

SIGSAND-EUROPE 2008: Proceedings of the 3rd AIS SIGSAND Euro...

引用

3rd AIS SIGSAND European symposium on Analysis, Design, Use and Societal Impact of Information systems, SIGSAND-EUROPE 2008

ISBN: (纸本)9783885792239

The proceedings contain 13 papers. The topics discussed include: boundary objects for value-based requirements engineering;capturing the semantics of quality requirements into an intermediate predesign model;design of fractal-based systems within MDA: platform independent modelling;reference model for service-oriented business software based on web service nets;relational model driven application design;OOLH: a formal framework for specifying system requirements;modelling complex events with event-driven process chains;SaferWeb - community driven collection of suitable websites for children;ambient information systems - do they open a new quality of is?;an investigation into the technology adoption paradox;MeBIT - an interdisciplinary project on ‘information’ metaphors and their impact on the idea of man;the impact of activity labeling styles on process model quality;and advanced reduction rules for the verification of EPC business process models.

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Parallel Implementation of Morphological Processing on Cell/BE with OpenCV Interface

Parallel Implementation of Morphological Processing on Cell/...

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3rd International symposium on Communications, Control, and Signal Processing (ISCCSP 2008), vol.2

作者： Hiroki Sugano Ryusuke Miyamoto Department of Communications and Computer Engineering Kyoto University Kyoto Japan Department of Information Systems Nara Institute of Science and Technology Ikoma Nara Japan

One of the most frequently used operations in image recognition is morphological processing. In this paper, we propose a parallel implementation of morphological processing optimized for Cell Broadband Engine (Cell), which is one of the latest high performance embedded processors. By utilizing the computational power of Cell suitable for image recognition, we achieve high-speed morphological processing. Moreover, we construct a software interface to the parallel implemented morphological operations on Cell compatible with OpenCV library. By our implementation, two 3.6 GHz SPEs on Cell can process erosion of a 1024×768 pixel image by a 5×5 pixel rectangle kernel in 0.601 milliseconds, though a 2.66 GHz Intel Core 2 processor takes 11.590 milliseconds to process it.

关键词： Image recognition software libraries Morphological operations Real time systems Concurrent computing Engines Pixel application software Embedded computing Open source software

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Current-Mode Filter in 65nm CMOS for a software-Radio application

Current-Mode Filter in 65nm CMOS for a Software-Radio Applic...

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2008 ieee International symposium on Circuits and systems (ISCAS 2008), vol.9

作者： Robert Kolm Weixun Yan Horst Zimmermann Institute for Electrical Measurements and Circuit Design University of Technology Vienna Vienna Austria

For the transmit path of a software radio defined system a 3rd-order current-mode filter in 65nm CMOS is presented. This filter consists of a 1st-order current-mode filter where a capacitance multiplication technique is applied. With this technique the needed capacitance is decreased by a factor of 2. The 2nd-order filter consists of an active gm-RC filter where the output voltage is also converted into a current. The filter has a switchable cut-off frequency of 1MHz and 4MHz, the current consumption is 5.26mA at V_(DD)velence1.2V and for an input current of 340(mu)A the THD is 1percent.

关键词： Filters application software Voltage CMOS technology Mirrors Capacitance Cutoff frequency Analog circuits Capacitors Signal processing

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A new battery and redundancy aware node scheduling protocol for Wireless Sensor Networks

A new battery and redundancy aware node scheduling protocol ...

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International Conference on Communication systems software and Middleware (COMSWARE)

作者： Ka. Selvaradjou M. Dhanaraj B. Goutham C. Siva Ram Murthy Department of Computer Science and Engineering Indian Institute of Technology Chennai India

Wireless Sensor Networks demand energy conserving protocols at all layers of protocol stack in order to achieve increased network lifetime. In this work, we propose a node scheduling protocol for sensor networks that exploits the battery charge recovery property and node level redundancy with respect to sensing, in order to maximize the network lifetime. The protocol forms a virtual grid and periodically elects the active node in a given grid. The primary battery sources of the remaining redundant nodes are completely switched off. The periodic election of active nodes ensures that every redundant node recovers its battery charges during their inactive period. We compare the performance of our protocol with baseline approaches like Strict Alternation, Periodic Alternation which are redundancy aware and also with the standard ieee 802.11 and T-MAC protocols. The simulation results reveal that our protocol achieves network lifetime as high as 20% to 40% than the other schemes, with un-interrupted sensing and reporting of the events to sink.

关键词： Batteries Wireless application protocol Wireless sensor networks Military computing Media Access Protocol Processor scheduling Monitoring Spread spectrum communication Sensor phenomena and characterization Computer science

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Low-Cost Bluetooth Mobile Positioning for Location-based application

Low-Cost Bluetooth Mobile Positioning for Location-based App...

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ieee/IFIP International Conference in Central Asia on Internet (ICI)

作者： M. Zaafir Barahim M. Razvi Doomun Nazrana Joomun Computer Science and Engineering Department University of Mauritius Reduit Mauritius

Bluetooth is a promising short-range radio network technology. We present a low cost and easily deployed, scalable infrastructure for indoor location-based computing of mobile devices based on the Bluetooth technology. The system consists of 2 main components, namely the Bluetooth (BT) Sensor System and the Central Navigation System which have been developed using the JDK 1.6. The Bluetooth Sensor System allows mobile devices whose Bluetooth mode is set to discoverable, to be scanned and detected, and they receive customizable text message and other relevant files (maps, sound files, video clips) of their positioning information, e.g. room identity. The positioning information is also sent to the Central Navigation System which in turn displays and updates the navigation map. The system is also used to track the movement of different BT mobile devices within the implemented environment.

关键词： Bluetooth Costs Mobile computing Computer science Navigation Indoor environments Sensor systems GSM application software Radio network

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Artificial Brain based on Brain-Inspired Algorithms for Human-Like Intelligent Functions

Artificial Brain based on Brain-Inspired Algorithms for Huma...

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ieee International Conference on Integration technology (ICIT)

作者： Soo-Young Lee Korea Advanced Institute of Science and Technology South Korea

The Korean Brain Neuroinformatics Research Program got into the 3rd phase from July 2004 for 4 years, which is regarded as the final phase of Korean brain national research program started from November 1998 for 10 years. It is a joint effort of researchers from many different disciplines including neuroscience, cognitive science, electrical engineering, and computer science, and currently about 35 Ph.D.s and about 70 graduate students are involved in the program. The Korean Brain Neuroinformatics Research Program has two goals, i.e., to understand information processing mechanisms in biological brains and to develop intelligent machines with human-like functions based on the mechanism. In the 3rd phase we are developing an integrated hardware and software platform for the brain-like intelligent systems, which combine all the technologies developed for the brain functions in the second phase. With 2 microphones, 2 cameras (or retina chips), and one speaker, the Artificial Brain looks like a human head, and has the functions of vision, auditory, cognition, and behavior. Also, with this platform, we plan to develop a testbed application, i.e., "artificial secretary" alias OfficeMate, which will reduce the working time of human secretary by a half. Each OfficeMate should have its own unique personality, which may be effected by its own previous states as well as the current input and output values of the Agent. We are modeling the personality as internal states, which are implemented by recurrent neural networks.

关键词： Artificial intelligence Machine intelligence Humans Neuroscience Cognitive science Electrical engineering Computer science Information processing Hardware Intelligent systems

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Optimizing the Fast Fourier Transform on a Multi-core Architecture

Optimizing the Fast Fourier Transform on a Multi-core Archit...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Long Chen Ziang Hu Junmin Lin Guang R. Gao Department of Electrical & Computer Engineering University of Delaware Newark DE USA Department of Computer & Technology Tsinghua University Beijing China

The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system software designers: how to best exploit the parallelism potential due to such multi-core architectures? In this paper, we report an in-depth study on such challenges based on our experience of optimizing the fast Fourier transform (FFT) on the IBM Cyclops-64 chip architecture - a large-scale multi-core chip architecture consisting 160 thread units, associated memory banks and an interconnection network that connect them together in a shared memory organization. We demonstrate how multi-core architectures like the C64 could be used to achieve a high performance implementation of FFT both in 1D and 2D cases. We analyze the optimization challenges and opportunities including problem decomposition, load balancing, work distribution, and data-reuse, together with the exploiting of the C64 architecture features such as the multi-level of memory hierarchy and large register files. Furthermore, the experience learned during the hand-tuned optimization process have provided valuable guidance in our compiler optimization design and implementation. The main contributions of this paper include: 1) our study demonstrates that successful optimization for C64-like large-scale multi-core architectures requires a careful analysis that can identify certain domain-specific features of a target application (e.g. FFT) and match them well with some key multi-core architecture features; 2) our optimization, assisted with hand-tuned process, provided quantitative evidence on the importance of each optimization identified in 1); 3) automatic optimization by our compiler, the design and implementation of which is guided by the feedbacks from 1) and 2), shows excellent results that are often comparable to the results derived from our time-consuming hand-tuned code.

关键词： Fast Fourier transforms Computer architecture Design optimization Optimizing compilers Large-scale systems Microprocessor chips Multicore processing application software System software software design

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