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检索条件"任意字段=3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997"

共 79 条记录，以下是71-80 订阅

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ILP architectures: trading hardware for software complexity 3

ILP architectures: trading hardware for software complexity

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： Corporaal, H Delft Univ Technol Dept Elect Engn NL-2628 CD Delft Netherlands

ISBN: (纸本)0780342291

Currently, several interesting superscalar and VLIW (very large instruction word) processors hit the market. These processors exploit so-called instruction level parallelism (ILP);each cycle multiple operations are executed. This paper analyzes the data path complexity of lLP processors;in particular of VLIWs. It demonstrates that their complexity gets out of control when scaling to very high performance. Several methods are researched for reducing this complexity. Essentially these methods trade hardware for software complexity, i.e., performing as much as possible at compile time. This results in a new architectural approach called transport triggering. Its concept and characteristics are outlined. The application of this concept results in a number of hardware advantages, and introduces several new scheduling optimizations.

关键词： Commerce

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Active expressions: A framework for concurrency 3

Active expressions: A framework for concurrency

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： De Simone, M Singh, A Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 2K3 Canada

ISBN: (纸本)0780342291

Active Expressions (A(e)) is a language-based model for the instantiation of type-safe concurrent applications. Using facilities included in modern object-oriented languages, Ae allows the definition of communication and synchronization patterns that, when combined with user provided functionality through well defined interfaces, instantiate complete concurrent applications. The approach has two unique characteristics: First, it shows that common patterns of concurrency can be expressed using language provided facilities. Second, the model can be implemented without requiring any complex user-interfaces, preprocessing stages or language extensions. It also shows that the pattern-based approach has the potential to reduce the complexity of developing concurrent applications.

关键词： User interfaces

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A parallel sort-balance mutual range-join algorithm on hypercube computers 3

A parallel sort-balance mutual range-join algorithm on hyper...

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： Wong, R Topor, R Shen, H Griffith Univ Sch Comp & Informat Technol Nathan Qld 4111 Australia

ISBN: (纸本)0780342291

This paper presents an efficient parallel algorithm for computing the mutual range-join of N sets of numbers on shared-nothing hypercube computers. The algorithm iteratively joins each set to the mutual range-join of the preceding sets. Each join is performed on all processors of the hypercube in parallel. The algorithm uses a global sorting method to distribute the elements of the first set evenly across all processors in increasing order, a new data balancing technique to distribute the elements of subsequent sets to match the intermediate set at each processor and to compensate for join skew, and a new efficient local range-join procedure. We analyse the performance of this algorithm and demonstrate that it improves on the best previously published algorithm for this problem when the join selectivity factor is small. The method can also be applied to similar problems such as band-join and equi-join.

关键词： relational database query evaluation range-join hypercube parallel algorithm

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Multiple dependent queries execution using critical path scheduling in parallel databases 3

Multiple dependent queries execution using critical path sch...

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： Liu, KH Leung, CHC Jiang, Y Victoria Univ Technol Dept Math & Comp Sci Footscray Vic Australia

ISBN: (纸本)0780342291

Multiple processors are employed to improve the performance of database systems and the parallelism can be exploited at three levels in query processing: intra-operation, inter-operation, and inter-query parallelism. Intra-operation and inter-operation parallelism are also called intra-query parallelism which has been studied extensively recently. In contrast inter-query parallelism has received little attention particularly for multiple dependent queries. In this paper, we develop a decompression algorithm, CPS, for coping with multiple dependent queries which are represented by a directed graph, and the algorithm makes use of the activity analysis of critical path analysis, and the resource scheduling and levelling of project management. A simulation study has been conducted and the results show that the proposed algorithm outperforms other existing methods and is able to provide a global optimal solution when the number of processors available is sufficient.

关键词： Query processing

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Generating communication sets efficiently on data-parallel programs 3

Generating communication sets efficiently on data-parallel p...

引用

3rd international conference on algorithms and architectures for parallel processing, ica3pp 1997

作者： Huang, Tsung-Chuan Shiu, Liang-Cheng Yu, Cherng-Haw Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan

ISBN: (纸本)0780342291

Generating local memory access sequences and communication sets efficiently is an important issue while compiling a data-parallel language into a SPMD (Single Program Multiple Data) code. Recently, several approaches have been presented;they are based on the case in which array references are distributed across arbitrary number of processors with arbitrary block sizes using block-cyclic distribution. Typically, in order to generate explicit communication sets, each node program has to scan over the local memory access sequences. In this paper, we focus on two cases. First, array references are aligned to a common template and this template is distributed across processors using block-cyclic distribution. Second, array references are distributed across the same number of processors with same block size. The first case is further classified into one-level and two-level mappings. We construct a block state graph to generate communication sets by scanning only a portion of local memory access sequence. In one-level mappings and the second case, we only need to scan the active elements among the first s local active blocks;while in two-level mappings, only need to scan the active elements among the first α∗s local active blocks, where s is the stride of regular section and a is the stride of alignment function. As a result, the efficiency can be greatly improved. © 1997 IEEE.

关键词： Mapping

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A new method for transparent fault tolerance of distributed programs on a network of workstations using alternative schedules 3

A new method for transparent fault tolerance of distributed ...

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： Das, D Dasgupta, P Das, pp Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)0780342291

In this paper, me devise a new method for transparent fault tolerance of distributed programs running on a cluster of networked workstations. We use the concept of alternative schedules for this purpose. Such schedules are generated from static task graphs at compile-time. At run-time a distributed program can use these alternatives to switch from one schedule to another if some machine/s become faulty. We have devised fast but efficient mechanisms for switching among schedules at run-time. This enables fault recovery from any number of simultaneous machine faults any number of times. The correctness of the resultant algorithm is ensured through prevention of direct data sharing among local tasks on a machine. Such a transparent fault tolerant strategy is easily implementable on a network of workstations running PVM-like softwares.

关键词： Fault tolerance

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parallel neural network training on Multi-Spert 3

Parallel neural network training on Multi-Spert

引用

3rd international conference on algorithms and architectures for parallel processing (ica(3)pp)

作者： Farber, P Asanovic, K Int Comp Sci Inst Berkeley CA 94704 USA

ISBN: (纸本)0780342291

Multi-Spert is a scalable parallel system built from multiple Spert-II nodes which we have constructed to speed error backpropagation neural network training for speech recognition research. We present the Multi-Spert hardware and software architecture, and describe our implementation of two alternative parallelization strategies for the backprop algorithm. We have developed detailed analytic models of the two strategies which allow us to predict performance over a range of network and machine parameters. The models' predictions are validated by measurements for a prototype five node Multi-Spert system. This prototype achieves a neural network training performance of over 530 million connection updates per second (MCUPS) while training a realistic speech application neural network. The model predicts that performance will scale to over 800 MCUPS for eight nodes.

关键词： Neural networks

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parallel implementation of synthetic aperture radar on high performance computing platforms 3

Parallel implementation of synthetic aperture radar on high ...

引用

3rd international conference on algorithms and architectures for parallel processing, ica3pp 1997

作者： Suh, Jinwoo Ung, M. Prasanna, V.K. Department of EE-Systems University of Southern California Los AngelesCA90089-2562 United States

ISBN: (纸本)0780342291

We show a high throughput implementation of SAR on high performance computing (HPC) platforms. In our implementation, the processors are divided into two groups of size M and N. The first group consisting of M processors computes the FDC (frequency domain convolution) in range dimension, and the second group of N processors computes the FDC in azimuth dimension. M and N are determined by the computational requirements of FDC in range and azimuth dimensions respectively. The key contribution of this paper is the development of a general high-throughput M-to-N communication algorithm. The M-to-N communication algorithm is a basic communication primitive used in many signal processing applications when a software task pipeline is employed to obtain high throughput performance. Our algorithm reduces the number of communication steps to 1g(N/M+1)+n(k-1), where k≥2 and n=[1gk M]. Implementation results on the IBM SP2 and the Cray T3D based on the MITRE real-time benchmarks are presented. The results show that, given an image of size 1K×1K, the minimum number of processors required for processing the SAR benchmarks can be reduced by 50% by using the proposed communication algorithm. © 1997 IEEE.

关键词： Synthetic aperture radar

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IEEE 3rd international conference on algorithms and architectures for parallel processing

引用

1997年

作者： IEEE Aerospace & Electronics Systems Society IEEE Victorian Section

ISBN: (纸本)9780780342293

From the Publisher: The ica pp-97 Proceedings comprises a well defined set of S papers in the area of parallel processing. Specific topics covered in the S include: basic issues of algorithms and architectures for parallel processing; parallel processing Prospects; routing in parallel Computer Systems; special-purpose parallel architectures; operating Environments; scheduling; parallelisation and parallelising Computers; computing on Clusters of Workstations; parallel algorithms; parallel Applications; parallel algorithms and architectures for Neural Program; databases and parallel processing. Held in Melbourne, Australia, this important conference brought together developers and researchers from universities, industry and government to advance the level of knowledge for parallel and distributed systems and processing.

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