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检索条件"任意字段=3rd International Conference on Circuits, System and Simulation, ICCSS 2019"

共 736 条记录，以下是51-60 订阅

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Analysis of Oscillation Characteristics Caused by Nonlinear Control of D-PMSG Grid Connected system

Analysis of Oscillation Characteristics Caused by Nonlinear ...

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Energy Engineering and Power systems (EEPS), international conference on

作者： Shaopu Tang Ruiqi Jiao Jiaqi Ma Department of Electrical Engineering Tsinghua University Beijing China

ISBN: (数字)9798350375138

ISBN: (纸本)9798350375145

The power oscillation of the new energy grid connected system has a significant impact on the stable operation of the system. This article analyzes the impact of nonlinear links in new energy grid connected systems on system power oscillations, such as control switching and amplitude limiting. The PMSG grid connected system adopts Type-4 structure, and the control switching logic and existing limiting links in each control link under normal and fault states are analyzed. Through system simulation calculation, the influence of system limiting links, control switching, and related control parameters on system power oscillation is analyzed.

关键词： Limiting Process control Switches Power system stability Control systems Stability analysis systems simulation Voltage control Oscillators Switching circuits

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A Novel Method for Modeling and Co-simulation of FPGA Package and Board

A Novel Method for Modeling and Co-Simulation of FPGA Packag...

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Power Electronics & IoT Applications in Renewable Energy and its Control (PARC), 2020 international conference on

作者： Lakshya Saini Ravinder Agarwal Surender Singh Thapar University Patiala India Cadence Design System Noida India

Field Programmable Gate Array (FPGA) circuits have become an integral part of recent embedded process control designs. However, printed circuit board (PCB) layout design has become increasingly challenging due to the various propagation delays associated with FPGA pin count. To compensate for these delays on the PCB side, high-speed PCB interconnect lines are left unmatched, making sign-off of the board a major challenge in the absence of an FPGA model. Unfortunately, FPGA vendors do not provide the behavior model of FPGA; instead, they give only the pin delay report in a comma-separated file format. This file format is not considered by most simulation tools during analysis and simulation, thus limiting signal data rates to 10 Gbps for board-level simulation. Timing violations arise in simulation results if the duration of these signals differs at the board level at these high data rates, and as a result, the board must be redrawn. This paper presents a novel methodology for creating FPGA models that incorporate package delay in the absence of accurate package models on the board, known as package co-simulation. A close-to-actual parametric spice model of the package is generated, which is tested on a high-speed FPGA board. The simulation results of the proposed package model are compared to the absence of the package model results, indicating that the interconnect delay inside the package is considered during board package *** methodology is a significant advancement in the field of FPGA circuit design, as it enables designers to create more accurate models of FPGA circuits and optimize PCB layout design while considering the propagation delays and package interconnect delays. It is expected that this methodology will be a valuable tool for future FPGA circuit designs, enabling designers to achieve a higher level of accuracy and efficiency.

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Performance Analysis of FBMC/OQAM system with Prototype Filter for Wireless Applications

Performance Analysis of FBMC/OQAM System with Prototype Filt...

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Integrated circuits and Communication systems (ICICACS), IEEE international conference on

作者： Satish Kanapala Shaik Jakeer Hussain Department of Electronics and Communication Engineering Vignan's Foundation For Science Technology and Research Guntur India

ISBN: (数字)9798331508456

ISBN: (纸本)9798331508463

The FBMC/OQAM system, an advanced form of multi-carrier modulation, offers enhanced spectral efficiency and improved resistance to multipath interference in noisy environments compared to the traditional OFDM system. As a result, it is gaining attention as a promising candidate for 5G mobile communications. A key performance metric for evaluating the FBMC/OQAM system is the Bit Error Rate (BER), which is influenced by signal to noise ratio (SNR), channel conditions, modulation techniques, and coding strategies. BER analysis helps identify the system's strengths and weaknesses, facilitating further design and performance optimization. Prototype filter design for FBMC/OQAM system is presented in this paper which shows the comparative analysis of its BER performance relative to the OFDM system. The results are intended to highlight the potential of FBMC/OQAM as a promising modulation technique for next-generation wireless communication networks.

关键词： Wireless communication Resistance Spectral efficiency OFDM simulation Bit error rate Prototypes Modulation Interference Signal to noise ratio

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An Interference Model of Sub-module Driver Circuit in MMC system 3

An Interference Model of Sub-module Driver Circuit in MMC Sy...

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3rd IEEE international Power Electronics and Application conference and Exposition, PEAC 2022

作者： Yang, Rui Chen, Boyu Qi, Nianzun Zhang, Zhihan Yang, Shunfeng Southwest Jiaotong University Department of Electrical Engineering Chengdu China

ISBN: (数字)9781665491419

ISBN: (纸本)9781665491419

The number of sub-modules in the MMC system is large, and in the operating state, the sub-module floating ground voltage generates high dv/dt along with the sub-module switching, which will cause EMI issues in the sub-module itself such as driver interference due to the existence of circuit parasitic parameters. In this paper, a driver interference model is established, a sub-module interference source model is built and simplified, and the sub-module power device driver loop is modeled and equivalent. the model is verified by simulation, and the influence of different parameters on the interference is analyzed. © 2022 IEEE.

关键词： Timing circuits

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Joint simulation of High Voltage Line Fault Based on ATPdraw and MATLAB

Joint Simulation of High Voltage Line Fault Based on ATPdraw...

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New Energy and Power Engineering (ICNEPE), international conference on

作者： Lifang Wang Shaohang Zhou Qingxue Liu Yue Huang School of Mechanical and Electrical Engineering Kunming University Kunming China China Oilfield Services Limited Tianjin China

A joint simulation method for high voltage line faults based on ATPdraw and MATLAB is presented in this paper. Firstly, ATPdraw software is used to establish a simulation model of the Dual-ended power supply system, setting the parameters of each component in the model and simulating the faults of single-phase ground short circuits, two-phase short circuit, two-phase grounding short circuit, and three-phase short circuit. Then, the waveform simulated by ATPdraw is imported into MATLAB software, and the waveform of each fault component is programmed and calculated. The results show that this method can accurately detect faults in high-voltage lines and has high computational efficiency and real-time performance. Therefore, the joint simulation method of high voltage line faults based on ATPdraw and MATLAB provides an effective and practical solution for transient analysis and protection of power systems.

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simulation and comfort evaluation on Pavement for wheelchair human body system 3

Simulation and comfort evaluation on Pavement for wheelchair...

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3rd international conference on Intelligent Design, ICID 2022

作者： Luo, Haitao Cao, Xuan Sun, Jiaze Kong, Xiangfeng School of Mechanical Engineering Shenyang Ligong University Shenyang110159 China Shenyang110016 China Institutes for Robotics and Intelligent Manufacturing Chinese Academy of Sciences Shenyang110169 China School of Mechanical Engineering Shenyang University of Technology Shenyang110142 China

ISBN: (数字)9781665476775

ISBN: (纸本)9781665476775

When the user drives the wheelchair on the road, the wheelchair receives the vibration brought by the road and transmits it to the human body. The vibration acts on the whole body of the human body and has an adverse effect on the comfort and physical and mental health of the human body. In order to efficiently evaluate the comfort of the human body when riding in a wheelchair, this study based on the existing wheelchair platform, established a wheelchair model through the multi-body dynamics software ADAMS, and used the biomechanical simulation plug-in Lifemod to establish a multi-degree-of-freedom(DOF) biomechanical model of the human body. Based on the above two Build a wheelchair-human multi-DOF simulation model. Through the simulation on the B-level standard road surface, the driving behavior of the system in this dynamic environment is analyzed, and the human comfort is evaluated. The results show that the wheelchair-human system has poor comfort on the lower back when driving on standard road surfaces, and is slightly uncomfortable, while the bottock and foot have good comfort. This method has certain advantages for quickly evaluating the riding comfort of the wheelchair-human system. It provides an effective method for predicting and evaluating human riding comfort in the design stage of wheelchair products. © 2022 IEEE.

关键词： Degrees of freedom (mechanics)

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A Novel High Step-Down DC-DC Converter Based On Symmetric PWM Half Bridge Converter

A Novel High Step-Down DC-DC Converter Based On Symmetric PW...

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Energy Engineering and Power systems (EEPS), international conference on

作者： Zhaolin Hao Runquan Meng Shanxi Key Lab of Power System Operation and Control Taiyuan University of Technology Taiyuan China

ISBN: (数字)9798350375138

ISBN: (纸本)9798350375145

This paper proposes a new ISOP (Input Series Output Quasi Parallel) resonant converter composed of LLC resonant converter and symmetrical half bridge PWM converter to address the limitations of the Buck converter in high conversion ratio conditions and its limited duty cycle adjustment, which is not suitable for situations such as data centers with electrical isolation and high safety performance requirements. It provides a new choice for different application scenarios and has certain advantages in low-voltage and high current output situations. The circuit structure of the converter is introduced, and its working principle and characteristics are analyzed. The correctness of the topology structure is verified through simulation on Simulink.

关键词： Pulse width modulation converters Software packages simulation Bridge circuits Resonant converters Pulse width modulation Topology Safety Voltage control Switching circuits

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Low-Power 8x8 S-RAM Memory Design: CADENCE-Based simulation and Analysis

Low-Power 8x8 S-RAM Memory Design: CADENCE-Based Simulation ...

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Innovation in Technology (INOCON), IEEE international conference for

作者： T O Geetharani Ramya H G Shreya L S Sonu S Y Department of ECE Siddaganga Institute of Technology Tumakuru India

Static random access memory (SRAM) and dynamic random access memory (DRAM) are two types of memory circuits that are important for system architecture and are related to power consumption. Memory usage can be reduced, thus improving reliability, performance and overall cost. Low-power SRAM is becoming increasingly important in many VLSI chips. Therefore, it is important to have a lower power SRAM that operates at a higher speed. The aim of this project is to design and simulate an 8x8 low-power SRAM memory array using Cadence tools. Initially, different topologies of SRAMs such as 6T, 7T, 8T and 9T were designed and analyzed in read and write mode. To build an SRAM memory array, different modules such as decoders, logic amplifiers, SRAM arrays, and multiplexers need to be designed and integrated. The performance of SRAM topologies was compared taking into account parameters such as propagation delay, static power consumption, static noise and corner analysis. The topology with the best performance is then considered for the low power implementation using Sleep technique.

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FPGA-Based Efficient Implementation of CBNS Computational circuits: A Modular Approach 3rd

FPGA-Based Efficient Implementation of CBNS Computational C...

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3rd international conference on Computational Advancement in Communication circuits and systems, ICCACCS 2020

作者： Mukherjee, Madhumita Sanyal, Salil Kumar Department of ETCE Jadavpur University Kolkata700032 India Department of ECE Narula Institute of Technology Agarpara Kolkata700109 India

ISBN: (纸本)9789811640346

Complex binary number system (CBNS) finds extensive applications in the faster computation of various digital signal processing (DSP) algorithms. In this paper, an attempt has been undertaken to develop various computational circuits based on CBNS for implementation in Spartan XC3S700A FPGA platform. The circuits have been designed following a modular approach. The designed modules involve simple logic gates leading ultimately to efficient implementation on FPGA. The codes for the modules have been developed using verilog hardware description language (HDL). Structural-level designs of nibble size CBNS adder, multiplier, and subtractor have been exclusively accomplished involving these modules. In the design of multiplier and subtractor, a new concept of sub-block has been introduced to efficiently utilize the limited input capability of the designed modules. The proposed design involves less hardware complexity, silicon area, and path delay compared to existing works. simulation results and performance metrics for all the three CBNS circuits have been included. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Field programmable gate arrays (FPGA)

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Generation and Implementation of Random Number Architecture using Difference Expansion for Digital circuits 3

Generation and Implementation of Random Number Architecture ...

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3rd international conference on Intelligent Computing, Instrumentation and Control Technologies, ICICICT 2022

作者： Devi, S Nithya Sasipriya, S. Dr. N.G.P. Institute of Technology Dept. of Electronics and Communication Engineering Coimbatore641048 India Sri Krishna College of Engineering and Technology Dept. of Electronics and Communication Engineering Coimbatore641008 India

ISBN: (数字)9781665410052

ISBN: (纸本)9781665410052

Unified logic and very large-scale integration (VLSI) circuitry have been created to generate random numbers from various distributions such as uniform, exponential, and Gauss distributions. An arithmetic iteration notion is used to implement several architectural levels in the proposed system. Fast speed, low power consumption, and great output accuracy make this random number generator ideal for communications systems and other models that need multi-distribution random numbers. The difference expansion approach and linear feedback shift register (LFSR) bit switching are recommended to generate random numbers. Besides this, the randomization is unpredictably random. Predictable binary sequences have been a major drawback of earlier randomization approaches. Differential characteristics construct the sequence and keep things simple in this technique. It also aims to simplify the circuit and use less energy. Power, delay, and a lookup table are used to make performance comparisons. The proposed architecture was tested and evaluated using Xilinx. simulation results demonstrate that the proposed model outperforms standard random generators using Slices, Area, and Look Up Tables. According to the research findings, the proposed Difference Expansion-based Random Generation (DERG) has reduced latency and consumes less power. © 2022 IEEE.

关键词： Random number generation

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