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Designing neuromorphic architectures: towards an ultra low power AI

Designing neuromorphic architectures: towards an ultra low p...

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international conference on Embedded & distributed Systems (EDiS)

作者： Pierre Boulet Laboratory CRIStAL University of Lille France

ISBN: (数字)9798350397543

ISBN: (纸本)9798350397550

In the “bio-inspired information processing” project of the IRCICA interdisciplinary institute, we tackle the scientific challenges of the emerging neuromorphic architectures. These computer architectures mimic the brain by handling the information as spike trains and by processing this information with spiking neural networks. They have a strong potential for ultra low power artificial intelligence. Based on our last 10 years of research, we will present the state-of-the-art of these architectures, the applications we focus on, and the scientific hot topics.

关键词： Computer architecture Low-power electronics Computer science Professional societies parallel processing Neuromorphic engineering Nanoelectronics

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Data Management Model to Program Irregular Compute Kernels on FPGA: Application to Heterogeneous distributed System 27th

Data Management Model to Program Irregular Compute Kernels o...

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27th international European conference on parallel and distributed Computing (Euro-Par)

作者： Lenormand, Erwan Goubier, Thierry Cudennec, Loic Charles, Henri-Pierre Univ Paris Saclay LIST CEA F-91191 Gif Sur Yvette France DGA Maitrise Informat BP 7 F-35998 Rennes France Univ Grenoble Alpes LIST CEA F-38000 Grenoble France

ISBN: (纸本)9783031061561;9783031061554

This paper presents a data management model targeting heterogeneous distributed systems integrating reconfigurable accelerators. The purpose of this model is to reduce the complexity of developing applications with multidimensional sparse data structures. It relies on a shared memory paradigm, which is convenient for parallel programming of irregular applications. The distributed data, sliced in chunks, are managed by a Software-distributed Shared Memory (S-DSM). The integration of reconfigurable accelerators in this S-DSM, by breaking the master-slave model, allows devices to initiate access to chunks in order to accept data-dependent accesses. We use chunk partitioning of multidimensional sparse data structures, such as sparse matrices and unstructured meshes, to access them as a continuous data stream. This model enables to regularize memory accesses of irregular applications, to avoid the transfer of unnecessary data by providing fine-grained data access, and to efficiently hide data access latencies by implicitly overlaying the transferred data flow with the processed data flow. We have used two case studies to validate the proposed data management model: General Sparse Matrix-Matrix Multiplication (SpGEMM) and Shallow Water Equations (SWE) over an unstructured mesh. The results obtained show that the proposed model efficiently hides the data access latencies by reaching computation speeds close to those of an ideal case (i.e. without latency).

关键词： distributed shared memory Field programmable gate array Irregular application

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A MVCC Approach to parallelizing Interoperability of Consortium Blockchain 22nd

A MVCC Approach to Parallelizing Interoperability of Consort...

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22nd international conference on parallel and distributed Computing, applications and Technologies (PDCAT 2021)

作者： Lin, Weiyi Qu, Qiang Ning, Li Fan, Jianping Jiang, Qingshan Chinese Acad Sci Shenzhen Inst Adv Technol Shenzhen Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Huawei Cloud Blockchain Lab Shenzhen Peoples R China

ISBN: (纸本)9783030967727;9783030967710

Driven in part of the rapid growth of consortium blockchain applications, blockchain interoperability becomes extremely essential to exchange transactional data among decentralized applications. To ensure the data integrity of transactions, the state-of-the-art studies of the blockchain interoperability apply data locks, which however severely decrease system efficiency. To boost interoperability performance, this paper proposes a novel approach based on multi-version concurrency control to parallelize interoperable transactions, which aims high transaction processing throughput while ensuring data integrity. The experimental evaluation with the Smallbank benchmark shows that the proposed method achieves up to 4x performance increase (in terms of processed transactions per second, TPS) compared with the existing methods, and moreover, it decreases the average latency with 58%.

关键词： Blockchain interoperability MVCC Data parallel Transaction integrity

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3rd international Symposium on Signal and Image processing, ISSIP 2020

3rd International Symposium on Signal and Image Processing, ...

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3rd international Symposium on Signal and Image processing, ISSIP 2020

ISBN: (纸本)9789813369658

The proceedings contain 16 papers. The special focus in this conference is on Signal and Image processing. The topics include: Deep Convolutional Neural Network-Based Diagnosis of Invasive Ductal Carcinoma;speaker Identification in Spoken Language Mismatch Condition: An Experimental Study;Ultrasound Image Classification Using ACGAN with Small Training Dataset;preface;Chaotic Ions Motion Optimization (CIMO) for Biological Sequences Local Alignment: COVID-19 as a Case Study;assessment of Eyeball Movement and Head Movement Detection Based on Reading;using Hadoop Ecosystem and Python to Explore Climate Change;a Brief Review of Intelligent Rule Extraction Techniques;the Effect of Different Feature Selection Methods for Classification of Melanoma;intelligent Hybrid Technique to Secure Bluetooth Communications;parallel Algorithm to find Integer k where a given Well-distributed Graph is k-Metric Dimensional;a Fog-Based Retrieval of Real-Time Data for Health applications;differential Evolution-Based Shot Boundary Detection Algorithm for Content-Based Video Retrieval;qutrit-Based Genetic Algorithm for Hyperspectral Image Thresholding.

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3D Electrical Impedance Tomography System for Real-Time Annular Multiphase Flow Metering 3

3D Electrical Impedance Tomography System for Real-Time Annu...

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3rd international conference on distributed Sensing and Intelligent Systems, ICDSIS 2022

作者： Tarek, Mohamed Meribout, Mahmoud Tiwari, Varun Kumar Department of Electrical and Computer Engineering Khalifa University Abu Dhabi United Arab Emirates

ISBN: (纸本)9781839538186

With the rapid progress of tomography systems, a need has emerged for innovation that can provide high accuracy measurements, fast acquisition rate, and low-cost robust systems for multi-phase flow and medical instruments. The main objective of this work is to design and implement a 3D Electrical Impedance Tomography (EIT) system to effectively monitor a multi-phase flow which consists of an annular flow comprising of an air-core of unknown diameter, surrounded by a liquid phase, such as oil and water mixture of high water-cut value. The system consists of an array of electrode sensors evenly distributed around the pipe confining the three-phase flow. Subsequently, a dedicated hardware module (GPU) is used to reconstruct these signals, captured from the sensors, into a 3D image of the flow by solving the forward-inverse problem. The annular flow is generated using a flow conditioner consisting of a swirl cage followed by a bluff body that generates vortices that push the high dense liquid phase to the outer side of the pipeline. The 3D EIT system is designed to accurately measure the gas liquid fraction and the liquid-liquid fraction and provide the 3D volume image of the flow. Hence, it can be utilized for pipeline and reservoirs characterization to achieve high efficiency, cost reduction, and safer production. The approach is to design a dedicated, highly parallel hardware architecture that can sustain the high computation complexity of the 3D EIT algorithm. Coincidentally, advanced software development tools are available to help effectively develop these parallel hardware algorithms. The main novelty is utilizing GPUs to outperform the existing real-time tomography hardware platforms, mainly based on Field Programmable Gate Array (FPGAs), which have the disadvantage of being less dense and feature lower precise arithmetic operations. Matrix multiplication and matrix inversion are considered the most intensive computation in Electric Impedance Tomography (EIT). T

关键词： Graphics processing unit

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Contributions to Accelerating a Numerical Simulation of Free Flow parallel to a Porous Plane

Contributions to Accelerating a Numerical Simulation of Free...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Claudio Schepke Roberta A. Spigolon José Rufino Cesar F. Da C. Cristaldo Glener L. Pizzolato Laboratory of Advances Studies in Computation (LEA) Federal University of Pampa (UNIPAMPA) Alegrete Brazil Research Centre in Digitalization and Intelligent Robotics (CeDRI) Laboratório Associado para a Sustentabilidade e Tecnologia em Regiões de Montanha (SusTEC) Instituto Politécnico de Bragancá Bragança Portugal Laboratory of Computational Fluid Dynamics and Atmospheric Turbulence (LFCTA) Federal University of Pampa (UNIPAMPA) Alegrete Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Flow models over flat porous surfaces have applications in natural processes, such as material, food, chemical processing, or mountain mudflow simulations. The development of simplified analytical or numerical models can predict characteristics such as velocity, pressure, deviation length, and even temperature of such flows for geophysical and engineering purposes. In this context, there is considerable interest in theoretical and experimental models. Mathematical models to represent such phenomena for fluid mechanics have continuously been developed and implemented. Given this, we propose a mathematical and simulation model to describe a free-flowing flow parallel to a porous material and its transition zone. The objective of the application is to analyze the influence of the porous matrix on the flow under different matrix properties. We implement a Computational Fluid Dynamics scheme using the Finite Volume Method to simulate and calculate the numerical solutions for case studies. However, computational applications of this type demand high performance, requiring parallel execution techniques. Due to this, it is necessary to modify the sequential version of the code. So, we propose a methodology describing the steps required to adapt and improve the code. This approach decreases 5.3% the execution time of the sequential version of the code. Next, we adopt OpenMP for parallel versions and instantiate parallel code flows and executions on multi-core. We get a speedup of 10.4 by using 12 threads. The paper provides simulations that offer the correct understanding, modeling, and construction of abrupt transitions between free flow and porous media. The process presented here could expand to the simulations of other porous media problems. Furthermore, customized simulations require little processing time, thanks to parallel processing.

关键词： Codes Temperature Computational modeling Computational fluid dynamics Media parallel processing Numerical simulation Mathematical models Numerical models Surface treatment

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distributed Work Stealing in a Task-Based Dataflow Runtime 14th

Distributed Work Stealing in a Task-Based Dataflow Runtime

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14th international conference on parallel processing and Applied Mathematics, PPAM 2022

作者： John, Joseph Milthorpe, Josh Strazdins, Peter Australian National University Canberra Australia Oak Ridge National Laboratory Oak RidgeTN United States

ISBN: (纸本)9783031304415

The task-based dataflow programming model has emerged as an alternative to the process-centric programming model for extreme-scale applications. However, load balancing is still a challenge in task-based dataflow runtimes. In this paper, we present extensions to the PaRSEC runtime to demonstrate that distributed work stealing is an effective load-balancing method for task-based dataflow runtimes. In contrast to shared-memory work stealing, we find that each process should consider future tasks and the expected waiting time for execution when determining whether to steal. We demonstrate the effectiveness of the proposed work-stealing policies for a sparse Cholesky factorization, which shows a speedup of up to 35% compared to a static division of work. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Data flow analysis

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CNS Lock: Compact NUMA-aware Lock with a Standard Interface

CNS Lock: Compact NUMA-aware Lock with a Standard Interface

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Brahmaiah Gandham Praveen Alapati École Centrale School of Engineering Mahindra University Hyderabad India

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

In recent years, multi-core systems with NonUniform Memory Access (NUMA) architectures are becoming prevalent. Multithreaded applications that execute on NUMA architectures play a pivotal role in getting better performance. The difficulties associated with multi-threaded applications are more pronounced because of compatibility issues with synchronization objects and the underlying NUMA architectures. Locks are fundamental synchronization primitives to avoid data races and achieve high performance in multi-core systems. With the increasing performance demands, locks have been refined and optimized with the architectural features of the NUMA systems. This paper proposes a novel synchronization object, namely CNS Lock (Compact NUMA-aware lock with a Standard interface) for NUMA systems. The CNS lock utilizes a single queue irrespective of the number of NUMA nodes and minimizes the number of atomic operations required for lock acquisition and release by prioritizing threads based on their NUMA node affinity. It considers the current thread’s NUMA node number to get the efficiency of a NUMA-aware design. CNS lock provides a standard interface to facilitate seamless integration into existing applications without knowing the internals. The CNS Lock strategically optimizes lock handovers and minimizes memory latency by employing a unified queue system across NUMA nodes. Our experimental results show that the CNS lock significantly outperforms the state-of-the-art locking mechanisms and makes it one of the essential tools of systems with NUMA architectures for better synchronization.

关键词： Multicore processing Instruction sets Memory architecture Handover Synchronization Spinning Resource management Standards

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Design of English Information Retrieval System Based on parallel Corpus

Design of English Information Retrieval System Based on Para...

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CIBDA 2022;3rd international conference on Computer Information and Big Data applications

作者： Huiqin Guo Tao Yu

ISBN: (纸本)9783800758760

With the development of research in the field of natural language processing, corpus especially parallel corpus, is playing an increasingly important role as a basic resource supporting natural language processing technology. This paper mainly studies the design of English information retrieval system based on parallel corpus. Aiming at the requirement of information retrieval system, this paper proposes an information retrieval method based on parallel corpus, designs a graphic information retrieval model and puts forward a system framework. This paper explores the relevant technology, detailed requirements and implementation principles and other aspects of corpuses by detailed description of corpus design, implementation and testing.

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On-the-Fly Calculation of Model Factors for Multi-paradigm applications 28th

On-the-Fly Calculation of Model Factors for Multi-paradigm A...

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28th international conference on parallel and distributed Computing (Euro-Par)

作者： Protze, Joachim Orland, Fabian Haldar, Kingshuk Koritzius, Thore Terboven, Christian Rhein Westfal TH Aachen IT Ctr Aachen Germany Univ Stuttgart HLRS Stuttgart Germany

ISBN: (纸本)9783031125973;9783031125966

Model factors provide initial insight into fundamental issues of parallel applications. These metrics elaborate beyond conventional HPC metrics to indicate whether an application suffers from systemic or local load imbalances, or high cost for synchronization or data transfer. The metrics are also useful to compare the parallel characteristics of different versions of the same application. This work proposes a model of separating the impact factors of different layered parallelism paradigms. In contrast to previous work in this area, we successfully separate all factors and can prove all efficiency values to be between 0 and 1. While we use MPI OpenMP as an example in this work, the general concepts also apply to layering other parallel programming paradigms. As a proof of concept, we present a tool that collects the necessary performance data and determines different critical paths in the execution without measurable runtime overhead. We evaluate the methodology with synthetic source code examples but also with a real-world application and an application using the latest or future MPI and OpenMP features in order to evaluate the methodology on applications with an overlap of asynchronous computation and communication at the highest possible concurrency.

关键词： Data transfer

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