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Boosting Performance of Iterative applications on GPUs: Kernel Batching with CUDA Graphs

Boosting Performance of Iterative Applications on GPUs: Kern...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Jonah Ekelund Stefano Markidis Ivy Peng KTH Royal Institute of Technology Sweden

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Graphics processing Units (GPUs) have become the standard in accelerating scientific applications on heterogeneous systems. However, as GPUs are getting faster, one potential performance bottleneck with GPU-accelerated applications is the overhead from launching several fine-grained kernels. CUDA Graph addresses these performance challenges by enabling a graph-based execution model that captures operations as nodes and dependence as edges in a static graph. Thereby consolidating several kernel launches into one graph launch. We propose a performance optimization strategy for iteratively launched kernels. By grouping kernel launches into iteration batches and then unrolling these batches into a CUDA Graph, iterative applications can benefit from CUDA Graph for performance boosting. We analyze the performance gain and overhead from this approach by designing a skeleton application. The skeleton application also serves as a generalized example of converting an iterative solver to CUDA Graph, and for deriving a performance model. Using the skeleton application, we show that when unrolling iteration batches for a given platform, there is an optimal size of the iteration batch, which is independent of workload, balancing the extra overhead from graph creation with the performance gain of the graph execution. Depending on workload, we show that the optimal iteration batch size gives more than $1.4 \times$ speed-up in the skeleton application. Furthermore, we show that similar speed-up can be gained in Hotspot and Hotspot3D from the Rodinia benchmark suite and a Finite-Difference Time-Domain (FDTD) Maxwell solver.

关键词： Graphics processing units Performance gain Boosting Skeleton Iterative methods Kernel Time-domain analysis Optimization Standards Finite difference methods

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Adaptive AI-based Decentralized Resource Management in the Cloud-Edge Continuum

Adaptive AI-based Decentralized Resource Management in the C...

引用

Euromicro conference on parallel, distributed and Network-Based processing

作者： Lanpei Li Jack Bell Massimo Coppola Vincenzo Lomonaco ISTI-CNR Pisa Italy Department of Computer Science University of Pisa Pisa Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

In the Cloud-Edge Continuum, dynamic infrastructure change and variable workloads complicate efficient resource management. Centralized methods can struggle to adapt, whilst purely decentralized policies lack global oversight. This paper proposes a hybrid framework using Graph Neural Network (GNN) embeddings and collaborative multi-agent reinforcement learning (MARL). Local agents handle neighbourhood-level decisions, and a global orchestrator coordinates system-wide. This work contributes to decentralized application placement strategies with centralized oversight, GNN integration and collaborative MARL for efficient, adaptive and scalable resource management.

关键词： Training Scalability Collaboration Reinforcement learning Organizations Dynamic scheduling Decentralized applications Graph neural networks Robustness Resource management

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NPB-PSTL: C++ STL Algorithms with parallel Execution Policies in NAS parallel Benchmarks

NPB-PSTL: C++ STL Algorithms with Parallel Execution Policie...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Júnior Löff Renato B. Hoffmann Arthur S. Bianchessi Leonardo Mallmann Dalvan Griebler Walter Binder Faculty of Informatics Università della Svizzera italiana (USI) Lugano Switzerland Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The C++ language continually evolves through formal specifications established by its standards committee, proposing new features to maintain $\mathrm{C}++$ as a relevant programming language while improving usability, performance, and portability across platforms. With the addition of parallel Standard Template Library (STL) algorithms in C++17, programmers can now leverage parallel processing capabilities via vendor-neutral parallel execution policies. This study presents an adaptation of the NAS parallel Benchmarks (NPB)—a well-established suite of applications for evaluating parallel architectures-by porting its sequential C-style code to use C++ STL abstractions and performance-portable parallelism features. Our goals are to (1) assess the suitability of C++ STL for scientific applications like the ones in the NPB and (2) provide a comparative performance and portability of STL algorithms’ parallel execution policies across different multicore architectures (x86 and AArch64). Results indicate that the performance of parallel STL algorithms is often close to that of optimized handwritten versions (OpenMP, Intel TBB, and FastFlow) on different architectures, with notable shortfalls. Across all NPB benchmarks, the STL algorithms’ geometric mean shows sequential execution times that are between 3.76% and $\mathrm{6. 9 \%}$ higher, while parallel executions may reach a geometric mean of up to $\mathrm{2 1. 2 1 \%}$ higher execution time.

关键词： parallel programming Multicore processing Software algorithms C++ languages Benchmark testing parallel processing Data structures Libraries Hardware Standards

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Concurrent FFT Execution on GPUs in Real-Time

Concurrent FFT Execution on GPUs in Real-Time

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Syed W. Ali Joseph Goh Joshua Bakita Samarjit Chakraborty James H. Anderson Department of Computer Science University of North Carolina at Chapel Hill

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Fourier transforms are vital for a broad range of signal-processing applications. Accelerating FFTs with GPUs offers an orders-of-magnitude improvement vs. CPU-only FFT computation. However, two problems arise when executing FFT tasks with other GPU work. First, concurrent GPU use introduces unpredictability in the form of lengthy response times. Second, it is unclear how to best parameterize and schedule FFT tasks to meet the throughput and timeliness constraints of real-time signal processing. This work investigates how FFT and other GPU-using tasks can concurrently access a GPU while maintaining bounded response-time guarantees without sacrificing throughput. In our experiments, the techniques proposed by this work result in an up to 17% improvement in worst-case FFT response times.

关键词： Schedules Accuracy Fast Fourier transforms Graphics processing units Signal processing Throughput Real-time systems Hardware Sensors Time factors

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An Anomaly Detection Model for RISC-V in Automotive applications: A Domain-Specific Accelerator Perspective

An Anomaly Detection Model for RISC-V in Automotive Applicat...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Elio Vinciguerra Enrico Russo Maurizio Palesi Giuseppe Ascia Department of Electrical Electronic and Computer Engineering University of Catania Catania Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Early anomaly detection in automotive systems is crucial for enhancing user safety and enabling timely corrective actions, thereby minimizing the risks associated with system malfunctions. This paper presents an approach for implementing Artificial Intelligence (AI)-based algorithms for anomaly detection in the automotive domain, leveraging the RISC-V architecture in conjunction with Domain-Specific Accelerators (DSAs). By exploiting the efficiency of DSAs, the proposed system aims to achieve faster anomaly detection compared to traditional processing methods. A detailed comparison is conducted between the performance of executing the AI-based anomaly detection algorithm on the RISC-V core versus offloading it to an optimized hardware accelerator tailored to the specific AI model. The goal of this work is to provide valuable insights into the potential of RISCV and DSAs to enhance AI-driven safety mechanisms, contributing to the development of more reliable automotive systems.

关键词： Program processors Neural networks Real-time systems Safety Reliability Artificial intelligence Anomaly detection Hardware acceleration Optimization Monitoring

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An Efficient Private Information Retrieval Protocol Based on TFHE 19th

An Efficient Private Information Retrieval Protocol Based on...

引用

19th international conference on Security and Privacy in Communication Networks

作者： Tian, Haibo Lin, Yini Sun Yat Sen Univ Sch Comp Sci & Engn Guangzhou 510006 Peoples R China Guangdong Prov Key Lab Informat Secur Technol Guangzhou 510006 Peoples R China

ISBN: (纸本)9783031649479;9783031649486

Private Information Retrieval (PIR) allows a user to query an entry from a database without revealing the index of the entry to the database owner. It is a building tool for many privacy enhancement applications, such as compromised credential checking and stock value query. However, the efficiency of PIR protocols has always been a bottleneck in their practical deployment. To address the challenge, we propose leveraging the fully homomorphic encryption over the torus (TFHE) scheme, which supports implementation on 32-bit unsigned integers and features a fast controlled selector (CMux) gate. The CMux gate can naturally construct a table lookup algorithm to serve PIR. We introduce compression and expansion algorithms for a PIR query, resulting in an encrypted query only a few hundred bytes in size. Further, we present a parallel PIR protocol and four simultaneous table lookup (STLU) algorithms based on TFHE, which are implemented on graphics processing units (GPUs) and make a distributed PIR service with a fast response time. On four servers with five GPUs, we obtain a PIR service with a response time of less than 2 seconds and a query size of less than 200 bytes on a database containing 2(22) entries, with each entry encoding a message of at least 256 bytes.

关键词： private information retrieval fully homomorphic encryption over the torus simultaneous table lookup graphics processing units

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Utilizing Network Hardware parallelism for MPI Partitioned Collective Communication

Utilizing Network Hardware Parallelism for MPI Partitioned C...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Yıltan Hassan Temuçin Amirreza Barati Sedeh Whit Schonbein Ryan E. Grant Ahmad Afsahi ECE Department Queen’s University Kingston ON Canada Sandia National Laboratories Albuquerque New Mexico USA

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

parallel distributed applications running on large-scale high-performance computing systems depend on effective point-to-point and collective communication to meet performance goals. Beginning with version 4.0, the Message Passing Interface (MPI) introduced the partitioned communication API, providing tools for addressing communication bottlenecks raised by hybrid communication models. This API allows individual actors (CPU threads, GPU threads, etc.) to initiate communication on portions of complete buffers, enabling additional communication/computation overlap. Intuitively, the utility of partitioned communication could benefit from network-level support: If there are multiple paths between endpoints, an MPI-aware network could disperse partitions across these paths, avoiding the data serialization entailed by a dependency on a single path. The Cerio Rockport Ethernet Fabric has the ability to expose this capability to communication middleware. In this work we develop this capability to allow for user-level path selection for MPI partitioned communication and explore how this capability impacts point-to-point performance, collective design, and Allreduce efficiency in a Large Language Model task

关键词： Message passing Large language models High performance computing Ethernet parallel processing Hardware Fabrics Libraries Middleware Message systems

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A Performance Analysis of Autovectorization on RVV RISC-V Boards

A Performance Analysis of Autovectorization on RVV RISC-V Bo...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Lorenzo Carpentieri Mohammad VazirPanah Biagio Cosenza Department of Computer Science University of Salerno Italy

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The RISC-V instruction set architecture has become increasingly popular due to its open source and extensible design, making it a competitive choice in high-performance computing and embedded systems. The RISC-V Vector extension (RVV) empowers RISC-V processors with length-agnostic vectorization capabilities, a critical feature for efficiently handling parallel processing demands across different hardware. Compiler support for autovectorization allows to generate vector instructions automatically without requiring any effort to programmers. Given the limited yet evolving compiler support for RVV, this paper offers an in-depth examination of autovectorization capabilities in GCC and LLVM, for RVV version 0.7 and 1.0. We evaluated the autovectorization performance of LLVM, LLVM-EPI and GCC compilers across 151 loops from the Test Suite for Vectorizing Compilers (TSVC) ans seven real-world applications on the AllWinner D1 and BananaPi-F3 boards, representing RISC-V vector hardware. Our study focuses on quantifying and comparing the level of vectorization each compiler achieves across a diverse range of vectorization patterns and workloads, providing insight into their strengths and limitations with respect to RISC-V RVV. Our findings highlight that the LLVM-19 compiler outperforms GCC-14 in 76 out of 151 loops, and its performance is more sensitive to the selection of vector length. Additionally, tuning the vector Length Multiplier (LMUL) parameter can lead to performance improvements of up to $3 x$, and leveraging knowledge of the vector length can further enhance LMUL optimization in compilers.

关键词： Embedded systems Instruction sets High performance computing parallel processing Vectors Hardware Registers Performance analysis Tuning Optimization

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HiPerConTracer 3.0: Transport-level Packet Routing Analysis Tool

HiPerConTracer 3.0: Transport-level Packet Routing Analysis ...

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Thomas Dreibholz Somnath Mazumdar Center for Resilient Networks and Applications Simula Metropolitan Norway Department of Digitalization Copenhagen Business School Denmark

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

Network-based applications rely on the underlying network infrastructure to reliably forward packets between nodes. The way packets are forwarded has a significant impact on service quality. Therefore, it is important to gain a better understanding of data packet routes. To obtain detailed information about network paths, continuous and long-term packet analysis is required. To achieve this, we present our open-source framework HiPerConTracer 3.0 for large-scale IP trace analysis. It performs Ping and Traceroute measurements to provide detailed insights into packet routes and packet timing by tracing routes between senders and receivers in public and private networks. Particularly, it runs its own measurements, without need to obtain data, or cooperation from, the underlying network service providers or remote server owners. Our tool supports large-scale data collection, storage, and post-processing stages. It supports easy-to-understand route visualization, round-trip time measurements, and hop counts. A proof-of-concept analysis revealed that packet route lengths can change drastically when traveling through unexpected countries, regions, and network operators.

关键词： Atmospheric measurements Data visualization Receivers Data collection Routing Particle measurements Timing Servers Reliability IP networks

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A Performance Model of In-Situ Techniques

A Performance Model of In-Situ Techniques

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Euromicro conference on parallel, distributed and Network-Based processing

作者： Yi Ju Nicolas Vidal Adalberto Perez Ana Gainaru Fred Suter Stefano Markidis Philipp Schlatter Scott Klaskyll Erwin Laure Max Planck Computing and Data Facility Oak Ridge National Laboratory Friedrich-Alexander-Universität Erlangen-Nürnberg KTH Royal Institute of Technology

ISBN: (数字)9798331524937

ISBN: (纸本)9798331524944

The computational capacity of High-Performance Computing (HPC) systems increases continuously with the rapid development of central processing units (CPUs) and graphic processing units (GPUs), while the in-/output (IO) subsystem develops relatively slowly and storage capacity is also limited. Data-intensive applications, which are designed to leverage the high computational capacity of HPC resources, typically generate a considerable amount of data for post-processing visualizations and data analytics. The limited IO speed and storage space could lead to constraints in the actual performance of these applications and, therefore, scientific discovery. In-situ techniques, where data is visualized/analysed while still in memory rather than through disk, can contribute to alleviating these problems as they can reduce or even fully avoid data writing/reading through the IO subsystem to/from storage. However, the overall efficiency of insitu techniques crucially depends on the characteristics of both the in-situ tasks and the applications, and the resource distribution among them. Therefore, choosing the right in-situ approach (synchronous, asynchronous, or hybrid) and resource allocation is essential to minimize overhead and maximize the benefits of concurrent execution. In this paper, we present a performance model of in-situ techniques to find the most beneficial in-situ approach and the preferred resource configuration. We verify the high accuracy of our approach with over 6800 measurements and provide use cases with different applications.

关键词： Lead acid batteries Data analysis Accuracy High performance computing Graphics processing units Data visualization Central processing Unit Resource management

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