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A space-efficient on-chip compressed cache organization for high performance computing 04

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Proceedings of the Second international conference on parallel and distributed processing and applications

作者： Keun Soo Yim Jang-Soo Lee Jihong Kim Shin-Dug Kim Kern Koh School of Computer Science and Engineering Seoul National University Seoul Korea IBM Poughkeepsie NY Department of Computer Science Yonsei University Seoul Korea

ISBN: (纸本)9783540241287

In order to alleviate the ever-increasing processor-memory performance gap of high-end parallel computers, on-chip compressed caches have been developed that can reduce the cache miss count and off-chip memory traffic by storing and transferring cache lines in a compressed form. However, we observed that their performance gain is often limited due to their use of the coarse-grained compressed cache line management which incurs internally fragmented space. In this paper, we present the fine-grained compressed cache line management which addresses the fragmentation problem, while avoiding an increase in the metadata size such as tag field and VM page table. Based on the SimpleScalar simulator with the SPEC benchmark suite, we show that over an existing compressed cache system the proposed cache organization can reduce the memory traffic by 15%, as it delivers compressed cache lines in a fine-grained way, and the cache miss count by 23%, as it stores up to three compressed cache lines in a physical cache line.

关键词： parallel processing internal fragmentation problem fine-grained management on-chip compressed cache processor-memory performance gap

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Designing a high performance and fault tolerant multistage interconnection network with easy dynamic rerouting 04

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Proceedings of the Second international conference on parallel and distributed processing and applications

作者： Ching-Wen Chen Phui-Si Gan Chih-Hung Chang Department of Computer Science and Information Engineering Chaoyang University of Technology Wufeng Taichung County Taiwan ROC

ISBN: (纸本)9783540241287

Designing a reliable and high performance multistage interconnection network (MIN) should consider the following issues carefully: (1) fault tolerance guarantee; (2) easy schemes and hardware design of rerouting switches; (3) low rerouting resulting in a low collision ratio. In this paper, we present the High Performance Chained Multistage Interconnection Network (HPCMIN) which has one-fault tolerance, destination tag routing for easy rerouting, one rerouting hop, resulting in a low collision ratio. From our simulation results, the HPCMIN results in a lower collision ratio than other dynamic rerouting networks. The HPCMIN is embedded with the indirect binary n-cube network(the ICube network) which is equivalent to many important MINs. Thus, the design methods used in the HPCMIN can be applied to these MINs so that they have the characteristics of the HPCMIN.

关键词： performance collision parallel computing multistage interconnection network (MIN) fault tolerance destination tag routing

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Learning from Wireless: a Prospective Approach to Human-Centered Computing

Learning from Wireless: a Prospective Approach to Human-Cent...

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international Joint conference on Neural Networks

作者： Yong Lu Shaohe Lv Xue Yang Xiaodong Wang Minne Li Xingming Zhou Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

ISBN: (纸本)9781509006212

One of the most important topics in Human-Centered Computing (HCC) is to recognise human's activities. In this paper, the technology of wireless-based activity recognition is introduced. By using wireless signals, one can achieve Non-Line-Of-Sight (NLOS) recognition without carrying any devices. Also, it is easy to deploy a wireless-based recognition system due to the ubiquity of wireless communication systems. The basic idea is to detect different characteristics of signal propagation that correspond to the distinct human behaviors. As a result, action recognition is performed by analyzing the distinguishable features of signal propagation. This paper introduces the basic principles and applications of wireless-based activity recognition, and discusses the challenges and related performance metrics. Finally, open problems are discussed to point out the future research trends.

关键词： Human-centered computing wireless Wireless communication systems Activity recognition recognition system Performance metrics signals Learning Paper Technology Human behavior

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Fault-Tolerant Cycle Embedding into 3-Ary n-Cubes with Structure Faults

Fault-Tolerant Cycle Embedding into 3-Ary n-Cubes with Struc...

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IEEE international conference on Big Data and Cloud Computing (BdCloud)

作者： Weibei Fan Yang Wang Jing Sun Zhijie Han Peng Li Ruchuan Wang Colledge of Computer Nanjing University of Posts and Telecommunications Nanjing China School of Computer and Information Engineering Henan University Kaifeng China

ISBN: (数字)9781728143286

ISBN: (纸本)9781728143293

3-Ary n-cube network, denoted by Q3 r, as the most important network topology in interconnection networks. It has been widely used because of its regular topology, low degree of nodes and easy implementation on a single chip. We study the cycle embedding into Q3 rwith structure faults, where each fault component is isomorphic to any connected subgraph of H1,3. Let M be a connected graph with M ϵ{W1,W1,1,W1,2,W1,3}. We prove that there is an arbitrary length cycle from 3 to |V (Q3/r - W)| if the faulty component is no more than r-1 and every fault component is isomorphic to any connected subgraph M, where W is the faulty components in an n-dimensional 3-ary n-cube. It is the first work which takes structure faults into account to study fault-tolerant pancyclicity of interconnection networks.

关键词： Multiprocessor interconnection Fault tolerance Fault tolerant systems Telecommunications Network topology parallel processing Program processors

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Semi-Supervised Generative Adversarial Model for 3D Recognition

Semi-Supervised Generative Adversarial Model for 3D Recognit...

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IEEE international Symposium on parallel and distributed processing with applications and IEEE international conference on Ubiquitous Computing and Communications (ISPA/IUCC)

作者： Haoqian Wang Shuhao Zhang Yongbing Zhang Zhihong Liu Key Laboratory of Broadband Network & Multimedia Graduate School at Shenzhen Tsinghua University Shenzhen China Shenzhen Institute of Future Technology Shenzhen China

ISBN: (纸本)9781728152103

In this paper, we focus on the issue of 3D point cloud recognition utilizing semi-supervised generative adversarial network, composed of two parts: classification net and generative adversarial net. Using the adversarial criterion, the generator learns to establish the mapping relationship from one-dimensional noise data to 3D point cloud, which can remedy the insufficient data available faced by traditional supervised methods, and the adversarial discriminator acts as a powerful 3D object descriptor to get the point cloud into the right category and eliminate the fake data brought by the generator. In order to fix the rotation problem of point cloud data and improve the recognition performance of the model, we also introduce the spatial transformation networks into the discriminator. Compared with the current supervised and unsupervised methods, the impressive experimental results we show illustrate the effectiveness of the proposed method.

关键词： image classification neural nets object recognition stereo image processing supervised learning Stereo image processing Neural network Semi-supervised Learning Image classification object recognition Clouds dynamos Recognition (Psychology)

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An FPGA distributed Implementation Model for Embedded SOM with On-Line Learning

An FPGA Distributed Implementation Model for Embedded SOM wi...

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international Joint conference on Neural Networks

作者： Miguel Angelo de Abreu de Sousa Emilio Del-Moral-Hernandez Department of Electronic Systems Engineering School of Engineering University of Sao Paulo

ISBN: (纸本)9781509061839

Neuroengineering has contributed to the increasing capability of embedded hardware to efficiently execute neural computation models. These hardware structures, suitable for implementing only the recall phase or both phases -learning and recall - of artificial neural networks (ANNs) are generally identified as neuromorphic systems. Some features of the FPGA technology resemble characteristics usually associated to ANNs, such as the parallel processing and the configurability of digital circuits. Embedded neural systems elaborated to execute Self-Organizing Maps (SOMs) can take advantage of the circuit parallelism to speed-up training process and also of the design flexibility by the hardware reconfiguration enabled by FPGA chips. Hardware-based SOMs capable of executing the training process on chip are relevant because they can be employed in a wide variety of stand-alone applications. IoT and mobile robotics are examples of some challenging research fields that use unsupervised learning to extract information from the surrounding environment and require the portability of embedded systems. This work presents a distributed architecture to implement SOM learning and recall algorithms into FPGAs. The distributed model does not employ any type of central control unit hence allowing a simple hardware redesign process during the configuration of the neural system. The set of experiments used for verifying the proposed architecture is specified in a data stream format. The aim of choosing streaming condition is to simulate applications in which the FPGA-based SOM must process a continuous flow of information autonomously. All the steps of the SOM learning algorithm to process an input sample are performed in a single clock cycle and implementation results show a maximum clock speed of 2.38 MHz. Synthesis reports on FPGA implementation of the distributed architecture for the experiments carried out herein also indicate that the factor of increase in consumption of chip reso

关键词： Embedded neural systems Self-Organizing Maps Neuromorphic hardware On-line learning FPGA self-organising feature maps Field programmable gate arrays GRHL3 gene clock frequency Artificial neural networks clock cycle recall Mental Recall

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Rammed, or What RAM3S Taught Us 20

Rammed, or What RAM3S Taught Us

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Proceedings of the 22nd international conference on Information Integration and Web-based applications & Services

作者： Ilaria Bartolini Marco Patella Alma Mater Studiorum Università di Bologna Department of Computer Science and Engineering - DISI Bologna Italy

ISBN: (纸本)9781450389228

RAM3S (Real-time Analysis of Massive MultiMedia Streams) is a framework that acts as a middleware software layer between multimedia stream analysis techniques and Big Data streaming platforms, so as to facilitate the implementation of the former on top of the latter. Indeed, the use of Big Data platforms can give way to the efficient management and analysis of large data amounts, but they require the user to concentrate on issues related to distributed computing, since their services are often too raw. The use of RAM3S greatly simplifies deploying non-parallel techniques to platforms like Apache Storm or Apache Flink, a fact that is demonstrated by the four different use cases we describe here. We detail the lessons we learned from exploiting RAM3S to implement the detailed use cases.

关键词： Stream processing Real-Time Analysis Big Data

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M-Guard: a new distributed deadlock detection algorithm based on mobile agent technology 04

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Proceedings of the Second international conference on parallel and distributed processing and applications

作者： Jingyang Zhou Xiaolin Chen Han Dai Jiannong Cao Daoxu Chen Dept. of Computer Science & Technology Nanjing Univ. Nanjing China Dept. of Computing Hong Kong Polytechnic Univ. Hong Kong China

ISBN: (纸本)9783540241287

Deadlock detection and resolution are of the fundamental issues in distributed systems. Although many algorithms have been proposed, these message passing based traditional solutions can hardly meet the challenges of the prevailing Internet computing and mobile computing. In this paper, we present a novel algorithm, namely the M-Guard, for deadlock detection and resolution in distributed systems based on mobile agent technology. The proposed algorithm lies in the intersection of the centralized type algorithm and the distributed type algorithm. An agent is employed in our algorithm as a guard with dual-role: when roaming in the system according to a specified itinerary algorithm, the agent collects resource request/allocation information for detecting deadlock cycles as well as propagating the collected network and resource information among the nodes. Consequently, accurate and timely detections of deadlocks can be made without any network node being the performance bottleneck. Preliminary simulation results show that, compared with several other algorithms, the M-Guard algorithm achieves both shorter deadlock persisting time and smaller phantom deadlock ratio. Moreover, the overall network communication overhead can be decreased, too.

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Stack and Queue Layouts for Toruses and Extended Hypercubes

Stack and Queue Layouts for Toruses and Extended Hypercubes

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Annual Hawaii international conference on System Sciences (HICSS)

作者： S. Bettayeb M. H. Heydari L. Morales I. H. Sudborough Department of Computer Science University of Houston Clear Lake Houston TX USA Department of Computer Science University of Texas Dallas Houston TX USA

Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses. Heath, Leighton, and Rosenberg showed that d-dimensional ternary hypercubes have stack number ¿,(N 1/9 ), with N=3 d nodes. Malitz showed that E edges implies stack number O(¿E). For k-ary d-dimensional hypercubes, with N = k d vertices, Malitz's bound is O(k d/2 ). We improve this to 2 d+1 -3. The 2 d+1 -3 bound holds for arbitrary d-dimensional toruses. The queue number of d-dimensional k-ary hypercubes or toruses is bounded by O(d). Hence, Heath, Leighton, and Rosenberg exhibit an exponential tradeoff between s(G) and q(G) for multidimensional ternary hypercubes. Conversely, they conjectured that, for any G, q(G) is O(s(G)). We present a family {H} of modified multidimensional toruses and conjecture that q(H) is not O(s(H)).

关键词： Hypercubes Multidimensional systems Computer science Upper bound Lakes Very large scale integration Books Application software Routing parallel processing

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Data Locality in Hadoop Cluster Systems

Data Locality in Hadoop Cluster Systems

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The 2014 10th international conference on Natural Computation (ICNC 2014) and the 2014 11th international conference on Fuzzy Systems and Knowledge Discovery (FSKD 2014)(第十届自然计算和第十一届模糊系统与知识发现国际会议)

作者： Mukhtaj Khan Maozhen Li Yang Liu School of Engineering and Design Brunel University Uxbridge Middlesex UB8 3PH UK School of Electrical Engineering and Information Systems Sichuan University 610065 China

ISBN: (纸本)9781479951499

MapReduce has become a major programming model that supports distributed and parallel processing for large-scale data-intensive applications such as web data mining,network traffic analysis,machine learning and scientific *** is the most popular open-source implementation of the MapReduce programming *** Hadoop,input files are divided into many data blocks and these blocks are distributed over several nodes in *** efficiently process the data blocks,Hadoop should provide an efficient scheduling mechanism for enhancing the performance of the system in a shared cluster *** Hadoop scheduling mainly caused by data locality issues due to limited network *** introducing the scheduling issues with regarding to the data locality,this paper review different data locality aware scheduling algorithms that handling the data locality *** addition,this paper also evaluating their features,strength,weakness and provided some guidelines on how to improve further these scheduling algorithms.

关键词： MapReduce,job scheduling,data locality.

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