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检索条件"任意字段=3rd International Symposium on Code Generation and Optimization"

共 319 条记录，以下是1-10 订阅

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Using quasi-oppositional butterfly optimization algorithm, a probabilistic optimal power flow for a combined tidal and electric vehicle renewable energy system

Using quasi-oppositional butterfly optimization algorithm, a...

引用

international symposium on Advanced Computing and Communication (ISACC)

作者： Arijit Chakraborty Dibakar Sarkar Arka Ghosal Sourav Paul Sneha Sultana Susanta Dutta Provas Kumar Roy Electrical Engineering Dr. B. C. Roy Engineering College Durgapur India Electrical Engineering Dr. B. C. Roy Engineering College Electrical Engineering Kalyani Government Engineering College Kalyani India

ISBN: (数字)9798331523893

ISBN: (纸本)9798331523909

Aiming to reduce operating expenses and emissions while satisfying system restrictions, optimal power flow, or OPF, is essential for effective and sustainable power system management. Quasi-Oppositional Based Learning (QOBL) is added to the butterfly optimization algorithm in this research to improve convergence and solution accuracy when solving the OPF issue. When tested on the IEEE 57-bus system, the suggested QOBOA outperforms current optimization methods in terms of transmission loss and voltage profile improvement. Combining renewable energy sources is crucial for efficient electricity generation because fossil fuel sources are becoming more and more improved every day. The suggested solutions integrate renewable energy sources, such as tidal and electric vehicles, to reduce the demand for fossil fuels in the generation of electricity. Furthermore, the suggested approach has a great deal of promise for improving the adaptability and resilience of contemporary power grids, particularly in light of the growing integration of decentralized energy resources (DERs) and renewable energy sources. This strategy can help future smart grid systems operate more effectively, sustainably, and dependably by facilitating quicker decision-making and enhancing the coordination of dispersed assets.

关键词： Renewable energy sources Uncertainty Electricity Voltage Propagation losses Probabilistic logic Fossil fuels Smart grids Usability Load flow

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Support Vector-Based Grey Wolf Optimizer for Optimal Scheduling of Generators in Thermal Power Plants

Support Vector-Based Grey Wolf Optimizer for Optimal Schedul...

引用

international symposium on Advanced Computing and Communication (ISACC)

作者： M Venkateswarlu Vadde Srikanth Kanike Krishna Barella Chakali Sanjeeva Kumar Department of EEE G. Pullaiah College of Engineering and Technology Kurnool Andhra Pradesh India

ISBN: (数字)9798331523893

ISBN: (纸本)9798331523909

In this study, an advanced Support Vector-based Grey Wolf Optimizer (SVGWO) is proposed for solving the Economic Load Dispatch (ELD) problem in thermal power systems. The ELD problem is inherently complex due to its non-convex and non-linear characteristics, making it a challenge for traditional optimization methods. The primary objective of this research is to minimize the total cost of power generation while ensuring that the load demands are met under operational constraints. The proposed methodology integrates Support Vector Machine (SVM) with the Grey Wolf Optimizer (GWO) to improve the search process by effectively navigating the solution space and enhancing convergence speed. The performance of the SVGWO is validated using standard test systems, including the IEEE 30-bus and IEEE 14-bus systems, under varying load demands. The results demonstrate the algorithm's ability to achieve significant cost reductions while maintaining a fast convergence rate. Comparative analysis with existing methods, highlights the superior performance of SVGWO in terms of cost minimization and robustness. The findings suggest that the SVGWO is an efficient and reliable tool for addressing complex ELD problems, offering a promising solution for improving economic efficiency in thermal power generation.

关键词： Support vector machines Costs Navigation Optimal scheduling Minimization Linear programming Robustness Power system reliability Power generation Convergence

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Automatic generation of high-performance trace compressors 05

Automatic generation of high-performance trace compressors

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3rd international symposium on code generation and optimization

作者： Burtscher, M Sam, NB Cornell Univ Comp Syst Lab Ithaca NY 14853 USA

ISBN: (纸本)076952298X

Program execution traces are frequently used in industry and academia. Yet, most trace-compression algorithms have to be re-implemented every time the trace format is changed, which takes time, is error prone, and often results in inefficient solutions. This paper describes and evaluates TCgen, a tool that automatically generates portable, customized, high-performance trace compressors. All the user has to do is provide a description of the trace format and select one or more predictors to compress the fields in the trace records. TCgen translates this specification into C source code and optimizes it for the specified trace format and predictor algorithms. On average, the generated code is faster and compresses better than the six other compression algorithms we have tested. For example, a comparison with SBC, one of the best trace-compression algorithms in the current literature, shows that TCgen's synthesized code compresses SPECcpu2000 address traces 23% more, decompresses them 24% faster, and compresses them 1029% faster.

关键词： Compressors Compression algorithms Prediction algorithms Laboratories Computer industry Computer errors Testing Writing Humans Registers

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Performance of runtime optimization on BLAST 05

Performance of runtime optimization on BLAST

引用

3rd international symposium on code generation and optimization

作者： Das, A Lu, JW Chen, H Kim, J Yew, PC Hsu, WC Chen, DY Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA

ISBN: (纸本)076952298X

optimization of a real world application BLAST is used to demonstrate the limitations of static and profile-guided optimizations and to highlight the potential of runtime optimization systems. We analyze the performance profile of this application to determine performance bottlenecks and evaluate the effect of aggressive compiler optimizations on BLAST We find that applying common optimizations (e.g. 03) can degrade performance. Profile guided optimizations do not show much improvement across the board, as current implementations do not address critical performance bottlenecks in BLAST In some cases, these optimizations lower performance significantly due to unexpected secondary effects of aggressive optimizations. We also apply runtime optimization to BLAST using the ADORE framework. ADORE is able to detect performance bottlenecks and deploy optimizations resulting in performance gains up to 58% on some queries using data cache prefetching.

关键词： Runtime Optimizing compilers Program processors Testing Computer science Microprocessors Application software Performance analysis Degradation Performance gain

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Maintaining consistency and bounding capacity of software code caches 05

Maintaining consistency and bounding capacity of software co...

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3rd international symposium on code generation and optimization

作者： Bruening, D Amarasinghe, S MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)076952298X

Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching frequently executed fragments of code provides significant performance boosts, reducing the overhead of translation and emulation and meeting or exceeding native performance in dynamic optimizers. One disadvantage of caching, memory expansion, can sometimes be ignored when executing a single application. However as optimizers and translators are applied more and more in production systems, the memory expansion from running multiple applications simultaneously becomes problematic. A second drawback to caching is the added requirement of maintaining consistency between the code cache and the original code. On architectures like IA-32 that do not require explicit application actions when modifying code, detecting code changes is challenging. Again, consistency can be ignored for certain sets of applications, but as caching systems scale up to executing large, modern, complex programs, consistency becomes critical. This paper presents efficient schemes for keeping a software code cache consistent and for dynamically bounding code cache size to match the current working set of the application. These schemes are evaluated in the DynamoRIO runtime code manipulation system, and operate on stock hardware in the presence of multiple threads and dynamic behavior, including dynamically-loaded, generated, and even modified code.

关键词： Software maintenance Application software Software tools Optimizing compilers Runtime Dynamic compiler Emulation Production systems Hardware Yarn

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Compiler managed dynamic instruction placement in a low-power code cache 05

Compiler managed dynamic instruction placement in a low-powe...

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3rd international symposium on code generation and optimization

作者： Ravindran, RA Nagarkar, PD Dasika, GS Marsman, ED Senger, RM Mahlke, SA Brown, RB Univ Michigan Dept EECS Ann Arbor MI 48109 USA

ISBN: (纸本)076952298X

Modem embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-pad memories lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. In this work, we focus on exploiting scratch-pad memories for storing hot code segments within an application. Static placement techniques focus on placing the most frequently executed portions of programs into the scratch-pad. However, static schemes are inherently limited by not allowing the contents of the scratch-pad memory to change at run time. In a large fraction of applications, the instruction memory footprints exceed the scratch-pad memory size, thereby limiting the usefulness of the scratch-pad. We propose a compiler managed dynamic placement algorithm, wherein multiple hot code sequences, or traces, are overlapped with each other in the scratch-pad memory at different points in time during execution. Special copy instructions are provided to copy the traces into the scratch-pad memory at run-time. Using a power estimate, the compiler initially selects the most frequent traces in an application for relocation into the scratch-pad memory. Through iterative code motion and redundancy elimination, copy instructions are inserted in infrequently executed regions of the code. For a 64-byte code cache, the compiler managed dynamic placement achieves an average of 64% energy improvement over the static solution in a low-power embedded microcontroller.

关键词： Dynamic compiler Hardware Energy consumption Microprocessors Energy management Software maintenance Switches Educational institutions Data engineering Power engineering and energy

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Optimizing address code generation for array-intensive DSP applications 05

Optimizing address code generation for array-intensive DSP a...

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3rd international symposium on code generation and optimization

作者： Chen, GL Kandemir, M Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)076952298X

The application code size is a critical design factor for many embedded systems. Unfortunately, most available compilers optimize primarily for speed of execution rather than code density. As a result, the compiler-gene rated code can be much larger than necessary. In particular in the DSP domain, the past research found that optimizing address code generation can be very important since address code can account for over 50% of all program bits. This paper presents a compiler-directed scheme to minimize the number of instructions to be generated to manipulate address registers found in DSP architectures. As opposed to most of the prior techniques that attempt to reduce the number of such instructions through careful address register assignment, this paper proposes modifying loop access patterns in array-intensive signal processing applications. In addition, it demonstrates how the proposed scheme can cooperate with a data layout optimizer for increasing its benefits further We also discuss how optimizations that target effective address code generation can conflict with data locality-enhancing transformations. We evaluate the proposed approach using twelve array-intensive embedded applications. Our experimental results indicate that the proposed approach not only leads to significant reductions in code size but also outperforms prior efforts on reducing code size of array-intensive DSP applications.

关键词： Digital signal processing Registers Application software Optimizing compilers Parallel processing Computer science Design engineering Embedded system Array signal processing Design optimization

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Research on the reactive power optimization of distribution network including DG

Research on the reactive power optimization of distribution ...

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2012 3rd IEEE international symposium on Power Electronics for Distributed generation Systems, PEDG 2012

作者： Wang, Wei Xu, Lijie Wang, Shidan Kong, Jun Geng, Jing School of Electrical Engineering Beijing Jiaotong University Beijing 100044 China Liaoyuan Power Supply Company Liaoyuan Jilin 136200 China

ISBN: (纸本)9781467320238

Based on the improved genetic algorithm, the mathematical model of reactive power optimization for electric power distribution system integrating with distributed generation (DG) is proposed in this paper. The active power output of DG and the reactive power compensation position are added as control variable to analyze the influence to the reactive power optimization when DG connected to the system. The test system is a 33-bus electric power distribution system, and the simulation result shows that the method proposed in this paper is helpful in reducing power losses while improving the voltage profiles. © 2012 IEEE.

关键词： Distributed power generation

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Collecting and exploiting high-accuracy call graph profiles in virtual machines 05

Collecting and exploiting high-accuracy call graph profiles ...

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3rd international symposium on code generation and optimization

作者： Arnold, M Grove, D IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)076952298X

Due to the high dynamic frequency of virtual method calls in typical object-oriented programs, feedback-directed devirtualization and inlining is one of the most important optimizations performed by high-performance virtual machines. A critical input to effective feedback-directed inlining is an accurate dynamic call graph. In a virtual machine, the dynamic call graph is computed online during program execution. Therefore, to maximize overall system performance, the profiling mechanism must strike a balance between profile accuracy, the speed at which the profile becomes available to the optimizer, and profiling overhead. This paper introduces a new low-overhead sampling-based technique that rapidly converges on a high-accuracy dynamic call graph. We have implemented the technique in two high-performance virtual machines: Jikes RVM and J9. We empirically assess our profiling technique by reporting on the accuracy of the dynamic call graphs it computes and by demonstrating that increasing the accuracy of the dynamic call graph results in more effective feedback-directed inlining.

关键词： Virtual machining Optimizing compilers System performance Cost function Frequency optimization methods High performance computing Object oriented programming Degradation Maintenance engineering

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A LDPC Convolutional code optimization Method for FTN Systems 3

A LDPC Convolutional Code Optimization Method for FTN System...

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3rd IEEE international Conference on Computer and Communications (ICCC)

作者： Wu, Zhanji Huang, Xin Beijing Univ Posts & Telecommun Beijing Peoples R China

ISBN: (纸本)9781509063529

Next-generation satellite communication requires high transmission efficiency and high reliability to provide subscribers with various services. To satisfy these requirements, we optimize low-density parity-check convolutional codes (LDPC CC) for faster-than-Nyquist (FTN) systems with good degree distributions, girth profile (GP) as well as good sliding-window girth (SWG). In this paper, we mainly investigate the time-invariant LDPC CC which can be a parent code of a low-density parity-check block code (LDPC BC). A comprehensive set of LDPC CC optimization algorithm for FTN systems is presented and the optimized LDPC CC for FTN system can achieve about 2.9dB gain compared with the LDPC BC from WiMAX standard.

关键词： low-density parity-check convolutional codes (LDPC CC) faster-than-Nyquist (FTN) iterative decoding

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