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检索条件"任意字段=3rd International Symposium on Code Generation and Optimization"

共 319 条记录，以下是81-90 订阅

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Importance of Power Flow and Load Analysis in Pre-Installation Power Systems

Importance of Power Flow and Load Analysis in Pre-Installati...

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international symposium on Multidisciplinary Studies and Innovative Technologies (ISMSIT)

作者： Enes Cengiz Cemal Yılmaz Ercan Nurcan Yılmaz Hamdi Tolga Kahraman Electrical Electronics Engineering Gazi University Ankara Turkey Software Engineering Karadeniz Technical University Trabzon Turkey

Electricity is indispensable for everyone. Many technological tools developed are powered by electricity. It is important that electrical energy is delivered to customers in a continuous and high-quality manner. For uninterrupted energy, the right infrastructure and the right design for the installation are required. An incorrect design during the installation phase will result in malfunctions that are difficult to correct after installation. Power generation and distribution should be realized with minimum cost but maximum efficiency. Optimal power flow (OPF) in power systems is essential for reliable and efficient operation of electrical networks. OPF, which is a basic optimization tool in the fields of operation and planning, plays an important role in the power system. The OPF tries to minimize both power distribution losses and the cost of power drawn from the substation without affecting voltage regulation. The expected results for load flow analysis are voltage magnitude, phase angle, actual and reactive power. In this study, the power flow model of a power system based on real data of 8 busbar of İzmir province is designed. Different scenarios have been applied for accurate analysis of the system.

关键词： Generators Load flow analysis Power system stability Power generation Power transmission lines

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Reliability Studies of a 10nm High-performance and Low-power CMOS Technology Featuring 3rd generation FinFET and 5th generation HK/MG

Reliability Studies of a 10nm High-performance and Low-power...

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IEEE international Reliability Physics symposium (IRPS)

作者： Rahman, Anisur Dacuna, Javier Nayak, Pinakpani Leatherman, Gerald Ramey, Stephen Intel Corp Log Technol Dev Qual & Reliabil 2501 NW 229th Ave Hillsboro OR 97124 USA

ISBN: (纸本)9781538654798

Development of an industry leading 10nm CMOS process technology with the highest reported drive currents and cell densities involved numerous enabling innovations, judicious choice of design rules, novel features, and most importantly a relentless pursuit of performance-reliability co-optimization. This paper reports that Intel's 10nm technology achieved scaling benefit over its preceding 14nm generation at matched or better transistor reliability. An elaborate study of the challenges to scaling is presented, which once addressed, enabled meeting aggressive technology reliability targets.

关键词： 10nm High-k metal gate Bulk FinFET Hot carrier injection Oxide breakdown

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CFDlang: High-level code generation for high-order methods in fluid dynamics 2018

CFDlang: High-level code generation for high-order methods i...

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3rd ACM international Workshop on Real World Domain Specific Languages (RWDSL)

作者： Rink, Norman A. Huismann, Immo Susungi, Adilla Castrillon, Jeronimo Stiller, Joerg Froehlich, Jochen Tadonki, Claude Tech Univ Dresden Dresden Germany PSL Res Univ MINES ParisTech Paris France

ISBN: (纸本)9781450363556

Numerical simulations continue to enable fast and enormous progress in science and engineering. Writing efficient numerical codes is a difficult challenge that encompasses a variety of tasks from designing the right algorithms to exploiting the full potential of a platform's architecture. Domain-specific languages (DSLs) can ease these tasks by offering the right abstractions for expressing numerical problems. With the aid of domain knowledge, efficient code can then be generated automatically from abstract expressions. In this work, we present the CFDlang DSL for expressing tensor operations that constitute the performance-critical code sections in a class of real numerical applications from fluid dynamics. We demonstrate that CFDlang can be used to generate code automatically that performs as well, if not better, than carefully hand-optimized code.

关键词： language (DSL) design code generation and optimization tensor expressions numerical methods computational fluid dynamics (CFD)

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Design and Analysis of On-Chip Spiral Inductors Using Automatic Generated Layouts through SKILL code 3

Design and Analysis of On-Chip Spiral Inductors Using Automa...

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3rd international Conference on Electrical, Electronics, Communication, Computer Technologies and optimization Techniques (IGEECCOT)

作者： Abhishek, K. Harini, K. Rachana, B. Sobhana, T. Dhanabal, R. Vellore Inst Technol Sch Elect Engn Dept Micro & Nanoelect Vellore Tamil Nadu India

ISBN: (纸本)9781538651308

Inductor is one of the most area hungry, yet an important component in the modern wireless devices of communication systems and various other electronic devices. In this paper two inductors are designed and studied to obtain optimum characteristic values of inductance (L), quality factor (Q) and self-resonant frequency (fsrf). Designing an inductor with high quality factor at high frequency and low area is a challenging task. In this paper, realization of two spiral inductor design is implemented using SKILL coding for automatic layout generation of the inductors which also saves design time. Spiral inductors modeled with equal and unequal width and spacing between the turns are studied. Electromagnetic simulations are carried out using ANSYS HFSS EM simulator. From the simulation results, it can be noted that an inductance of 1.45 nH with a quality factor of 2.54 at 26.4 GHz is achieved for equal width and spacing. Whereas, the other inductor with unequal width and spacing results in an inductance of 3.55 nH with a quality factor of 9.43 at a frequency of 5.8 GHz. From the tabulated results, it is found that the unequal width and spacing between the turns gives higher quality factor.

关键词： inductance layout optimization quality factor SKILL coding

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ACM international Conference Proceeding Series

ACM International Conference Proceeding Series

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3rd ACM international Workshop on Real World Domain Specific Languages, RWDSL 2018. In conjunction with the international symposium on code generation andoptimization, CGO 2018

ISBN: (纸本)9781450363556

The proceedings contain 7 papers. The topics discussed include: industrial experience with the migration of legacy models using a DSL;dsmodels: a little language for dynamical systems;Saiph: towards a DSL for high-performance computational fluid dynamics;CFDlang: high-level code generation for high-order methods in fluid dynamics;D'Artagnan: an embedded DSL framework for distributed embedded systems;a task-based DSL for microcomputers;and Q#: enabling scalable quantum computing and development with a high-level DSL.

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NB-IoT optimization on Paging MCS and Coverage Level 15

NB-IoT Optimization on Paging MCS and Coverage Level

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15th international symposium on Wireless Communication Systems, ISWCS 2018

作者： Chung, Haheon Lee, Sunguk Jeong, Junho Mobile Access Network Technology Department Korea Telecom Seoul Korea Republic of

ISBN: (纸本)9781538650059

With growing popularity of Internet of Things (IoT), Low Power Wide Area (LPWA) technologies are getting more interests. Narrowband Internet of Things (NB-IoT) is a LPWA technology specified by 3rd generation Partnership Project (3GPP) and in the initial stage of commercialization. The performance of NB-IoT network needs to be optimized in downlink as well as uplink for reliable quality of NB-IoT services. In this paper, we provide optimization cases of modulation and coding scheme (MCS) for paging in multicell interference environments in terms of paging success rate in NB-IoT downlink. We also present optimization cases of coverage level (CL) in a commercial NB-IoT network environment with various driving speed in terms of random access channel (RACH) success rate in NB-IoT uplink. © 2018 IEEE.

关键词： Internet of things

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Development of a transmission-mounted power control unit including 12-volt DC-DC converter for 3rd generation Two-Motor Hybrid Systems 31

Development of a transmission-mounted power control unit inc...

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31st international Electric Vehicle symposium and Exhibition, EVS 2018 and international Electric Vehicle Technology Conference 2018, EVTeC 2018

作者： Kobori, Toshimitsu Tomokage, Ryoji Honda R and D Co. Ltd. Automobile R and D Center 4630 ShimotakanezawaHaga-machi Haga-gunTochigi321-3393 Japan

Proposed a third-generation power Control Unit (PCU) for a two-motor hybrid system. Up to now, the 12-volt DC-DC Converter (DCDC) was located in intelligent Power Unit (IPU), but by the built-in DCDC to PCU, it contributed the size down of IPU (-32% over size down) compared to a second-generation. We also introduced the downsizing technology of PCU. Specifically, the shrink of the Power module by the change of die bonding material, the reactor size down by the Voltage Control Unit (VCU) method change, and the optimization technology of the cooling structure was introduced. It realizes the DCDC built-in without PCU size up. Copyright © 2018 Society of Automotive Engineers of Japan, Inc. All rights reserved

关键词： DC-DC converters

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Comparison of runtime performance optimization using template-metaprogramming 3rd

Comparison of runtime performance optimization using templat...

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3rd international Conference on Next generation Computing Technologies, NGCT 2017

作者： Patel, Vivek Mishra, Piyush Patni, J.C. Mittal, Parul University of Petroleum and Energy Studies Dehradun248007 India

ISBN: (纸本)9789811086564

Programs capable of generating code are known as meta-programs and the technique of writing these programs is known as meta programming Meta programming is supported by various programming languages such as C#, where reflection is used;Ruby allows defining classes and methods at runtime using meta-programming;the first language to introduce the concept of meta-programming was LISP. The meta-programs written using these languages are generally parsers, theorem proofs and interpreters. In this paper, we’ll be demonstrating the use of meta-programming in C++ through template meta-programming (TMP). We pick up common mathematical operations, creating a run time code of them along with a compile time based equivalent code done through TMP. The two set of codes are then benchmarked on the basis of their execution time and a bar-graph is generated to compare the TMP and non-TMP programs. © Springer Nature Singapore Pte Ltd. 2018.

关键词： Benchmarking

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Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning

Hardware-Software Co-Design for an Analog-Digital Accelerato...

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3rd IEEE international Conference on Rebooting Computing (ICRC)

作者： Ambrosi, Joao Ankit, Aayush Antunes, Rodrigo Chalamalasetti, Sai Rahul Chatterjee, Soumitra El Hajj, Izzat Fachini, Guilherme Faraboschi, Paolo Foltin, Martin Huang, Sitao Hwu, Wen-mei Knuppe, Gustavo Lakshminarasimha, Sunil Vishwanathpur Milojicic, Dejan Parthasarathy, Mohan Ribeiro, Filipe Rosa, Lucas Roy, Kaushik Silveira, Plinio Strachan, John Paul Hewlett Packard Enterprise 1500 Page Mill Rd Palo Alto CA 94304 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781538691700

The increasing deployment of machine learning at the core and at the edge for applications such as video and image recognition has resulted in a number of special purpose accelerators in this domain. However, these accelerators do not have full end-to-end software stacks for application development, resulting in hard-to-develop, proprietary, and suboptimal application programming and executables. In this paper, we describe software stack for a memristor-based hybrid (analog-digital) accelerator. The software stack consists of an ONNX converter, an application optimizer, a compiler, a driver, and emulators. The ONNX converter helps leveraging interoperable neural network models developed on frameworks that support ONNX, such as CNTK, Caffe2, Tensorflow, etc. The application optimization layer adapts these interoperable models to the underlying hardware. The compiler generates executable ISA code that the underlying accelerator can run. Finally, the emulator enables software execution without actual hardware which enables hardware design space exploration and testing. By building a software stack, we have made hybrid memristor-based ML accelerators more accessible to software developers, enabled a generation of better-performing executables, and created an environment that can be leveraged by a multitude of existing neural network models developed using other frameworks to target these accelerators.

关键词： Software Hardware Computer architecture Encoding Computational modeling Registers optimization

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Proceedings of SPIE - The international Society for Optical Engineering

Proceedings of SPIE - The International Society for Optical ...

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3rd international Workshop on Pattern Recognition, IWPR 2018

ISBN: (纸本)9781510622685

The proceedings contain 55 papers. The topics discussed include: outlier detection algorithm based on robust component analysis;global contrast saliency detection of images with small scale structure suppression;robust vanishing point detection based on block wise weighted soft voting scheme;fast infrared image segmentation method based on 2D OTSU and particle swarm optimization;aesthetic QR code generation with background contrast enhancement and user interaction;glandular cavity segmentation based on local correntropy-based K-means (LCK) clustering and morphological operations;statistical multi-scale laws' texture energy for texture segmentation;and the denoising semi-coupled dictionary learning for retina image super-resolution.

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