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Reactive scripts

Reactive scripts

引用

IEEE international Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： F. Boussinot L. Hazard CMA École des Mines de Paris Sophia-Antipolis France CNET PAA/TSA France-Télécom Issy-Les-Moulineaux France

Reactive scripts are designed to get a flexible approach for responsive systems; they are based on the reactive/synchronous approach, well suited to real time programming. A reactive script interpretor is a broadcast event-driven interpreter which can react to several commands in parallel. Generating events and waiting for occurrence of events are the basic commands which are composed in several ways to build complex behaviors. The basic principle is that absence of an event cannot be decided before the end of the current interpretor reaction. One can define objects with associated methods (behaviors), run when a nonblocking order is sent to them. Method execution is immediate (in the same interpreter reaction as the order) and a method can be executed at most once during each reaction. Reactive scripts are a mix of two formalisms: the SL synchronous language, and the ROM Reactive Object Model. Reactive script interpreters are implemented using the Reactive-C language.

关键词： Parallel processing Yarn Dynamic programming Hazards Read only memory Scheduling Prototypes Concurrent computing logic programming Parallel programming

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Meta-programming in logic: Third international workshop, META-92 Uppsala, Sweden, June 10-12, 1992 Proceedings 3rd

引用

3rd international workshop on Meta-programming in logic, META 1992

作者： Pettorossi, Alberto University of Rome Tot Vergata Via della Ricerca Scientifica Roma1-00133 Italy

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Rough, Rougher, Roughest Extending EL with a Hierarchy of Indiscernibility Relations

Rough, Rougher, Roughest Extending EL with a Hierarchy of In...

引用

37th international workshop on Description logics, DL 2024

作者： Peñaloza, Rafael Turhan, Anni-Yasmin IKR3 Research Lab University of Milano-Bicocca Milan Italy Knowledge Representation Group Paderborn University Germany

Rough sets use a partition of a base set induced by a given indiscernibility relation p. In practice such partitions can result from clustering the data. DLs with concept operators relying on a single p for upper and lower approximations of concepts have been investigated so far. The use of a hierarchy of such equivalence relations as it can result from hierarchical clustering methods is not explored yet in a DL setting. In this paper we extend the rough DL ELpT with a hierarchy of indiscernibility relations as and develop a decision procedure for testing subsumption. © 2024 Copyright for this paper by its authors.

关键词： Hierarchical clustering

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1st international Joint Conference on Automated Reasoning, IJCAR 2001

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1st international Joint Conference on Automated Reasoning, IJCAR 2001 co-located with 3rd workshop on Inference in Computational Semantics, ICoS 2001 and 9th Symposium on the Integration of Symbolic Computation and Mechanized Reasoning, CALCULEMUS 2001

ISBN: (纸本)3540422544

The proceedings contain 59 papers. The special focus in this conference is on Description, Modal and Temporal logics. The topics include: Program termination analysis by size-change graphs;SET cardholder registration;algorithms, datastructures and other issues in efficient automated deduction;NExpTime-complete description logics with concrete domains;exploiting pseudo models for TBox and ABox reasoning in expressive description logics;the inverse method implements the automata approach for modal satisfiability;deduction-based decision procedure for a clausal miniscoped fragment of FTL;tableaux for temporal description logic with constant domains;free-variable tableaux for constant-domain quantified modal logics with rigid and non-rigid designation;instructing equational set-reasoning with otter;NP-completeness of refutability by literal-once resolution;ordered resolution vs. connection graph resolution;a model-based completeness proof of extended narrowing and resolution;a resolution-based decision procedure for the two-variable fragment with equality;superposition and chaining for totally ordered divisible abelian groups;on the evaluation of indexing techniques for theorem proving;preferred extensions of argumentation frameworks;bunched logic programming;a top-down procedure for disjunctive well-founded semantics;a second-order theorem prover applied to circumscription;a system for non-monotonic reasoning with logic programs under answer set semantics;conditional pure literal graphs;evaluating search heuristics and optimization techniques in propositional satisfiability;a system for deciding quantified boolean formulas satisfiability;a disconnection calculus theorem prover;more on implicit syntax;termination and reduction checking for higher-order logic programs;integrating connection-based theorem proving into interactive proof assistants and the extended least number heuristic.

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A True 6F2 NOR Flash Memory Cell Technology - Impact of Floating Gate B4-Flash on NOR Scaling

A True 6F2 NOR Flash Memory Cell Technology - Impact of Floa...

引用

IEEE international Memory workshop (IMW)

作者： S. Shimizu S. Shukuri N. Ajika T. Ogura M. Mihara Y. Kawajiri K. Kobayashi M. Nakashima GENUSION Inc. Amagasaki Hyogo Japan

This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate NOR cell. 6F2 B4-Flash cells featuring a self-aligned STI and self aligned contact architectures have been fabricated by a 90nm process and was confirmed sufficient performance for NOR array operation. The cell size of 0.0486um2 of 90nm 6F2 is the smallest NOR cell in the 90nm generation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than for conventional CHE programming cells, consequently gate length has been scaled down to 78nm.

关键词： Microprocessors logic gates programming Nonvolatile memory Junctions Arrays

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Transformations of signed-binary number representations for efficient VLSI arithmetic

Transformations of signed-binary number representations for ...

引用

IEEE international workshop on System-on-Chip for Real-Time Applications

作者： B.D. Andreev E.L. Titlebaum E.G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester NY USA

The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. Redundant arithmetic has received increasing interest in the past decade to reduce or eliminate carry propagation chains. The development of an analytical framework that expands the scope of functions that can be efficiently implemented using signed-binary representation is discussed in this paper. Implementation details are described that demonstrate the application of these results. Particular attention is placed on realizing the (a + b), -(a + b), (a - b), and -(a - b) functions in a complex /spl plusmn/1 multiplier serving as a pseudonoise code scrambler in wireless CDMA transceivers.

关键词： Very large scale integration Digital arithmetic Adders Delay logic circuits Multiaccess communication Transceivers Contracts Degradation Power dissipation

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Safe and efficient elimination of infeasible execution paths in WCET estimation

Safe and efficient elimination of infeasible execution paths...

引用

IEEE international Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： A.A. Kountouris IRISA Rennes France

Reasoning about the timing properties of a program is indispensable in the development of time critical systems where failure to meet deadlines can result in loss of life or material. To this end having tools to calculate safe and tight Worst Case Execution Time (WCET) bounds can be very valuable. In most of the approaches to date a lot of pessimism is attributed to the fact that many paths that are infeasible are not excluded from the WCET computations. To remedy this, user annotations to the source code were proposed and used. Unfortunately, there is no guarantee that these annotations are always correct. This fact renders such a manual approach unacceptable in the case of R/T systems where safety is an absolute priority. In this paper another approach for the safe elimination of infeasible execution paths is presented. This method is based on the R/T programming language SIGNAL and its internal Dynamic Graph representation.

关键词： Timing Safety Computer languages Program processors Equations Dynamic programming Predictive models Optimizing compilers Sufficient conditions Microarchitecture

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High Performance THANVaS Memories for MLC Charge Trap NAND Flash

High Performance THANVaS Memories for MLC Charge Trap NAND F...

引用

IEEE international Memory workshop (IMW)

作者： A. Suhane G. Van den bosch A. Arreghini L. Breuil A. Cacciato M. B. Zahid I. Debusschere K. De Meyer J. Van Houdt Imec Leuven Belgium ESAT KU Leuven Leuven Belgium

In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO 2 capping layer on top of the AI 2 O 3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO 2 capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10 4 cycles and improved high temperature retention.

关键词： logic gates Transient analysis Charge carrier processes Performance evaluation Aluminum oxide programming

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Study of Pass-Gate Voltage (VPASS) Interference in Sub-30nm Charge-Trapping (CT) NAND Flash Devices

Study of Pass-Gate Voltage (VPASS) Interference in Sub-30nm ...

引用

IEEE international Memory workshop (IMW)

作者： Yi-Hsuan Hsiao Hang-Ting Lue Kuo-Pin Chang Chih-Chang Hsieh Tzu-Hsuan Hsu Kuang-Yeu Hsieh Chih-Yuan Lu Emerging Central Laboratory Macronix International Company Limited Hsinchu Taiwan

For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold voltage decreases significantly with increasing VPASS during reading, contrary to the common believe that CT NAND devices are immune to the interference. We clarify that this extraordinary effect becomes significant for the scaled CT NAND Flash, where a lightly doped junction or junction-free device allows the fringing field caused by VPASS to penetrate into the selected cell and affects the inversion electron density. A small S/D junction recess or a non-cut ONO WL profile is suggested to minimize such effect. Moreover, we also find that the programming speed also decreases when a smaller VPASS PGM is applied. Based on our findings we suggest to use low-K spacer material between WL-WL in order to have better short-channel effect, lower interference and larger memory window for further scaling to sub-20 nm node.

关键词： Interference programming Flash memory Junctions logic gates Subthreshold current Conferences

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An ontology-based graphical tool for intelligent instruments

An ontology-based graphical tool for intelligent instruments

引用

IEEE international Conference on Computational Intelligence for Measurement Systems and Applications (CIMSA)

作者： R. Dapoigny P. Barlatier E. Benoit L. Foulloy LISTIC Université de Savoie Annecy-le-vieux France CNAM LYON Lyon France

This paper proposes a structured graphical method which relates both functional and behavioral requirements and software specifications to a detailed software design and implementation of intelligent instruments. The logic-based architecture is especially appropriate during the stage of conceptual design when modeling functional and behavioral specifications of digital instrumentation and control system are under consideration. The graphical representation of physical, functional and behavioral requirements is described through a multilayer hierarchical decomposition resulting from ontological analysis. As a consequence, the clear description of both goals and behavior for intelligent instruments within a single system that are based on first order logic axioms included in the ontology, allows one (with focussing on the teleological aspect of intelligent instruments) to enhance the model quality and to improve behavior reliability for intelligent instruments at run-time. The hierarchical decomposition (i) expresses semantic interrelations between the physical system and the behavioral items (ii) addresses incomplete or inconsistent requirements (iii) provides a structured framework that can serve as a basis for further extent. The system conceptualization is implemented in a new graphical tool resulting from the aggregation of object oriented software modules written in JAVA. The graphical tool is also referenced as Graphical CAPTool (GCAPTool).

关键词： Ontologies Instruments Object oriented modeling Software design Intelligent structures Computer architecture Control system synthesis Digital control Nonhomogeneous media logic

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