Reactive scripts are designed to get a flexible approach for responsive systems; they are based on the reactive/synchronous approach, well suited to real time programming. A reactive script interpretor is a broadcast ...
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Reactive scripts are designed to get a flexible approach for responsive systems; they are based on the reactive/synchronous approach, well suited to real time programming. A reactive script interpretor is a broadcast event-driven interpreter which can react to several commands in parallel. Generating events and waiting for occurrence of events are the basic commands which are composed in several ways to build complex behaviors. The basic principle is that absence of an event cannot be decided before the end of the current interpretor reaction. One can define objects with associated methods (behaviors), run when a nonblocking order is sent to them. Method execution is immediate (in the same interpreter reaction as the order) and a method can be executed at most once during each reaction. Reactive scripts are a mix of two formalisms: the SL synchronous language, and the ROM Reactive Object Model. Reactive script interpreters are implemented using the Reactive-C language.
Rough sets use a partition of a base set induced by a given indiscernibility relation p. In practice such partitions can result from clustering the data. DLs with concept operators relying on a single p for upper and ...
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The proceedings contain 59 papers. The special focus in this conference is on Description, Modal and Temporal logics. The topics include: Program termination analysis by size-change graphs;SET cardholder registration;...
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(纸本)3540422544
The proceedings contain 59 papers. The special focus in this conference is on Description, Modal and Temporal logics. The topics include: Program termination analysis by size-change graphs;SET cardholder registration;algorithms, datastructures and other issues in efficient automated deduction;NExpTime-complete description logics with concrete domains;exploiting pseudo models for TBox and ABox reasoning in expressive description logics;the inverse method implements the automata approach for modal satisfiability;deduction-based decision procedure for a clausal miniscoped fragment of FTL;tableaux for temporal description logic with constant domains;free-variable tableaux for constant-domain quantified modal logics with rigid and non-rigid designation;instructing equational set-reasoning with otter;NP-completeness of refutability by literal-once resolution;ordered resolution vs. connection graph resolution;a model-based completeness proof of extended narrowing and resolution;a resolution-based decision procedure for the two-variable fragment with equality;superposition and chaining for totally ordered divisible abelian groups;on the evaluation of indexing techniques for theorem proving;preferred extensions of argumentation frameworks;bunched logicprogramming;a top-down procedure for disjunctive well-founded semantics;a second-order theorem prover applied to circumscription;a system for non-monotonic reasoning with logic programs under answer set semantics;conditional pure literal graphs;evaluating search heuristics and optimization techniques in propositional satisfiability;a system for deciding quantified boolean formulas satisfiability;a disconnection calculus theorem prover;more on implicit syntax;termination and reduction checking for higher-order logic programs;integrating connection-based theorem proving into interactive proof assistants and the extended least number heuristic.
The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target fun...
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The VLSI implementation of arithmetic operations may be significantly improved by using non-conventional number representations and transforming intermediate results from one format to another format. For a target function, the objective is to change the number representations of the input and output operands such that a minimum amount of logic circuitry is required to achieve a computation. Redundant arithmetic has received increasing interest in the past decade to reduce or eliminate carry propagation chains. The development of an analytical framework that expands the scope of functions that can be efficiently implemented using signed-binary representation is discussed in this paper. Implementation details are described that demonstrate the application of these results. Particular attention is placed on realizing the (a + b), -(a + b), (a - b), and -(a - b) functions in a complex /spl plusmn/1 multiplier serving as a pseudonoise code scrambler in wireless CDMA transceivers.
Reasoning about the timing properties of a program is indispensable in the development of time critical systems where failure to meet deadlines can result in loss of life or material. To this end having tools to calcu...
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Reasoning about the timing properties of a program is indispensable in the development of time critical systems where failure to meet deadlines can result in loss of life or material. To this end having tools to calculate safe and tight Worst Case Execution Time (WCET) bounds can be very valuable. In most of the approaches to date a lot of pessimism is attributed to the fact that many paths that are infeasible are not excluded from the WCET computations. To remedy this, user annotations to the source code were proposed and used. Unfortunately, there is no guarantee that these annotations are always correct. This fact renders such a manual approach unacceptable in the case of R/T systems where safety is an absolute priority. In this paper another approach for the safe elimination of infeasible execution paths is presented. This method is based on the R/T programming language SIGNAL and its internal Dynamic Graph representation.
This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate ...
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This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate NOR cell. 6F2 B4-Flash cells featuring a self-aligned STI and self aligned contact architectures have been fabricated by a 90nm process and was confirmed sufficient performance for NOR array operation. The cell size of 0.0486um2 of 90nm 6F2 is the smallest NOR cell in the 90nm generation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than for conventional CHE programming cells, consequently gate length has been scaled down to 78nm.
In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO 2 capping layer on top of the AI 2 O 3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TAN...
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In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO 2 capping layer on top of the AI 2 O 3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO 2 capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10 4 cycles and improved high temperature retention.
Data-oriented workflows are often used in scientific applications for executing a set of dependent tasks across multiple computers. We discuss how these can be modeled using lambda calculus, and how ideas from functio...
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Data-oriented workflows are often used in scientific applications for executing a set of dependent tasks across multiple computers. We discuss how these can be modeled using lambda calculus, and how ideas from functional programming are applicable in the design of workflows. Such an approach avoids the restrictions often found in workflow languages, permitting the implementation of complex application in logic and data manipulation. This paper explains why lambda calculus is an appropriate model for workflow representation, and how a suitably efficient implementation can provide a wide range of capabilities to developers. The presented approach also permits high-level workflow features to be implemented at user level, in terms of a small set of low-level primitives provided by the language implementation. Copyright (C) 2009 John Wiley & Sons, Ltd.
For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold volta...
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For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold voltage decreases significantly with increasing VPASS during reading, contrary to the common believe that CT NAND devices are immune to the interference. We clarify that this extraordinary effect becomes significant for the scaled CT NAND Flash, where a lightly doped junction or junction-free device allows the fringing field caused by VPASS to penetrate into the selected cell and affects the inversion electron density. A small S/D junction recess or a non-cut ONO WL profile is suggested to minimize such effect. Moreover, we also find that the programming speed also decreases when a smaller VPASS PGM is applied. Based on our findings we suggest to use low-K spacer material between WL-WL in order to have better short-channel effect, lower interference and larger memory window for further scaling to sub-20 nm node.
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