This paper proposes a structured graphical method which relates both functional and behavioral requirements and software specifications to a detailed software design and implementation of intelligent instruments. The ...
详细信息
This paper proposes a structured graphical method which relates both functional and behavioral requirements and software specifications to a detailed software design and implementation of intelligent instruments. The logic-based architecture is especially appropriate during the stage of conceptual design when modeling functional and behavioral specifications of digital instrumentation and control system are under consideration. The graphical representation of physical, functional and behavioral requirements is described through a multilayer hierarchical decomposition resulting from ontological analysis. As a consequence, the clear description of both goals and behavior for intelligent instruments within a single system that are based on first order logic axioms included in the ontology, allows one (with focussing on the teleological aspect of intelligent instruments) to enhance the model quality and to improve behavior reliability for intelligent instruments at run-time. The hierarchical decomposition (i) expresses semantic interrelations between the physical system and the behavioral items (ii) addresses incomplete or inconsistent requirements (iii) provides a structured framework that can serve as a basis for further extent. The system conceptualization is implemented in a new graphical tool resulting from the aggregation of object oriented software modules written in JAVA. The graphical tool is also referenced as Graphical CAPTool (GCAPTool).
In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The p...
详细信息
ISBN:
(纸本)076951944X
In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. In others the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. Finally, an asynchronous array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 /spl mu/m CMOS technology, the simulation result of the maximum throughput is about 2.5 ns.
A new FPGA design using nonvolatile configuration memory (NCM) has been presented. NCM with large On/Off resistance ratio, such as nanoionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is ...
详细信息
A new FPGA design using nonvolatile configuration memory (NCM) has been presented. NCM with large On/Off resistance ratio, such as nanoionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Unlike previous FPGAs with nonvolatile programmable wires, we took architecture based approach for designing memory cell, since the cell area of programmable wire cell becomes larger than conventional SRAM-based configuration memory. We designed high-density NCM layout to evaluate the area reduction of configuration memory and verified the area of NCM is about 3.8X smaller than that of SRAM-based configuration memory, while it is 19X larger in the case of the programmable wire than SRAM-based one. It is expected that NCM achieved about over 20% reduction in total FPGA area. Area reduction of configuration memory also shortens the interconnect length to reduce the interconnect delay. Furthermore, nonvolatility achieves low power consumption with power gating.
Decision support systems play an important role in medical fields as they can augment clinicians to deal more efficiently and effectively with complex decision-making processes. In the diagnosis of headache disorders,...
详细信息
We show a 90nm nanocrystal-based split gate embedded flash memory that is able to meet the speed, endurance and reliability requirements for 32-bit microcontroller products. A 3.4V operating window is achievable and t...
详细信息
We show a 90nm nanocrystal-based split gate embedded flash memory that is able to meet the speed, endurance and reliability requirements for 32-bit microcontroller products. A 3.4V operating window is achievable and the process is robust and repeatable across many lots. Erase after 10k cycles can be achieved in 5ms, long-term data retention of cycled arrays is not susceptible to SILC-induced charge loss mechanisms, and program disturb can meet the needs of flash and EEPROM.
暂无评论