This paper presents novel contributions to the field of process mining in programmablelogic Controllers (PLCs). One significant contribution is the proposal of a new event source for process mining, which can be used...
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ISBN:
(纸本)9789819712731;9789819712748
This paper presents novel contributions to the field of process mining in programmablelogic Controllers (PLCs). One significant contribution is the proposal of a new event source for process mining, which can be used when PLC logs are absent or insufficient. This research also demonstrated the feasibility of converting the memory states of PLCs into event logs, which can be used to construct a process model of the PLC. This approach requires neither detailed knowledge about control logic nor source code of PLC. The paper also evaluates the use of process confrontation as a means of detecting abnormal or cyber-attacks on PLCs, which can provide an effective method for identifying abnormal behaviors and deviations from the normal process flow. Finally, the paper explores other optimization ideas for process mining in PLCs, provides useful insights, and offers potential solutions for extending research in this area.
With the transition of industries to automation, programmablelogic Controllers (PLCs) have become a central unit for control engineering. Industries have also started using Energy Monitoring systems seeking to identi...
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作者：
Nedaei, AmirEskandari, ArefPourshahbaz, NimaSalehpour, SherkoParvin, ParvizLivera, AndreasMakrides, GeorgeAghaei, Mohammadreza
Department of Electrical Engineering Tehran Iran
Department of Electrical Engineering Tehran Iran
Department of Physics and Energy Engineering Tehran Iran
PHAENTON Centre of Excellence for Intelligent Efficient and Sustainable Energy Solutions PV Technology Laboratory Department of Electrical and Computer Engineering Nicosia Cyprus
PHAETHON Centre of Excellence for Intelligent Efficient and Sustainable Energy Solutions PV Technology Laboratory Department of Electrical and Computer Engineering Nicosia Cyprus
Department of Ocean Operations and Civil Engineering Ålesund Norway
Freiburg Germany
Environmental and other stresses are constantly affecting photovoltaic (PV) components which can end in various faults. The anomalous condition can reduce the PV output power or even result in a calamitous fire hazard...
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Field programmable Gate Arrays (FPGAs) represent a category of integrated circuits and also semiconductor devices like these offer a wide range of functionalities. They are aptly named as 'field programmable' ...
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The secondary system plays important roles in a smart substation in order to ensure its intelligence performance and operational safety. The design of the secondary system results in SCD, SDD, and GIM files for its lo...
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ISBN:
(纸本)9798350375145;9798350375138
The secondary system plays important roles in a smart substation in order to ensure its intelligence performance and operational safety. The design of the secondary system results in SCD, SDD, and GIM files for its logic, physical and 3D models, respectively. But it is often challenging for engineers to map GOOSE signals onto 3D components of fiber ports. In this regard, a signal mapping method has been developed for associating 3D port with both the input and output GOOSE signals which are represented by the virtual pins. Finally, a case of a cubicle has been studied for validating the feasible application of the developed mapping method. This mapping information can assist maintenance engineers in decision-making for fault diagnosis and maintenance operations.
In order to improve the frequency of phaselocked loop (PLL), a high-speed divider-by-4/5 and 8/9 dual modulus prescaler are proposed. The speed of the prescaler is improved on two levels. At the top level, the propose...
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ISBN:
(纸本)9798350310801
In order to improve the frequency of phaselocked loop (PLL), a high-speed divider-by-4/5 and 8/9 dual modulus prescaler are proposed. The speed of the prescaler is improved on two levels. At the top level, the proposed work reaches high speed with the multiplier, logic gates, and synchronous divider-by-2/3 prescaler. At the gate level, speed optimization is achieved by TSPC DFF embedded with a logic gate. Fabricated in SMIC 0.13-mu m CMOS process, the frequency of the proposed circuit ranges from 500M to 8.5G. The power consumption is 1.16 mW at the maximum operating frequency under 1.2 V supply voltage.
This project explores the development and implementation of an automated RYB (Red, Yellow, Blue) color mixing process utilizing programmablelogic Controllers (PLCs). The objective is to design a robust and efficient ...
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This paper mainly designs a remote manipulator control system based on programmablelogic controller and Internet of Things technology. The system uses Siemens PLC as the robot controller and the Internet of Things de...
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The study of cryptography techniques on Field programmable Gate Array needs extensive research attention. Evaluation Boards is one such area of hardware security measures. An encryption algorithm must be developed on ...
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Neural Radiance Fields (NeRF) has shown its superiority in various fields, including 3D reconstruction and inverse rendering. However, due to its high computational demands, NeRF typically requires implementation on h...
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ISBN:
(纸本)9798350341515
Neural Radiance Fields (NeRF) has shown its superiority in various fields, including 3D reconstruction and inverse rendering. However, due to its high computational demands, NeRF typically requires implementation on high-performance GPUs, which is costly and power-intensive, thus limiting its applicability. Compared to GPUs, FPGAs offer a potential solution to implement NeRF at lower cost and power. However, FPGA-based NeRF designs are still rare. To address this issue, a novel hardware NeRF accelerator based on Xilinx UltraScale and UltraScale+ FPGA has been proposed. The proposed design is based on the Multiresolution Hash Encoding NeRF algorithm and comprises Feature Reader, Multilayer Perceptrons (MLP), and Volume Renderer. The Feature Reader and MLP calculate the coordinates and directions of the sampling points on the rays, which are then used to determine the colors and densities of these points. To prevent timing problems and routing congestion caused by high DSPs utilization, we use registers and cascade paths between DSPs to construct MACC matrices in MLP. The Volume Renderer processes these colors and densities to obtain the colors of rays. The proposed accelerator runs at 300MHz on Xilinx Alveo U250, achieving an average 1.60x performance improvement compared to NVIDIA GTX 1080 Ti. Additionally, the accelerator has reduced energy consumption per image by an average of 5.21x and 4.64x compared to NVIDIA GTX 1080 Ti and NVIDIA RTX 3090, respectively.
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