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Fuzzy logic Based Power Train Controller For Different Hybrid Electric Vehicle Configurations

Fuzzy Logic Based Power Train Controller For Different Hybri...

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Intelligent Technologies (CONIT), International conference on

作者： Rinku Garg Ashish Sharma Kanchan Yadav Manpreet Kaur Arti Rana University Institute of Computing Chandigarh University Mojhali Punjab Department of Electrical Engineering Chandigarh University Mohali India Department of Electrical Engineering GLA University Mathura India Department of CSE Gulzar Group of Institutions Khanna India Department of CSE UIT Uttranchal University Dehradun India

The most important contribution made by this study is the proposal of a fuzzy logic global power management strategy for hybrid electric vehicles powered by the machine Electric powertrain. This has been investigated from three different vantage points throughout the process. The first challenge is finding the optimal distribution of power between all of the internal combustion engines. The second step is to maximise the amount of potential energy that can be absorbed by the vehicle while it is braking. Finally, a dependable ON/OFF controller of the Internal Combustion Engine (ICE) implements a State of Charge (SOC) maintenance strategy for the battery. In order to accomplish these goals, the development of three different fuzzy logic (FL) controllers was necessary. The level of charge in the battery, the speed of the vehicle, the traction torque, and the amount of power that is required are all used in the creation of the FL controllers. In order to integrate the researched system, the simulation model technique is utilised. This technique is founded on the programmable MATLAB/Simulink environment. In this paper, a Fuzzy logic Controller (FLC) is proposed as a means of providing optimal switching and controlling of Hybrid Electric Vehicles (HEV). FLC is utilised so that the desired speed can be attained from the Motor or IC Engine in a very short amount of time. The distribution of power between the ICE and the EM is the most important aspect of the fuzzy logical controller (FLC). In addition, the size and weight of electrical components like inverters and batteries can be significantly reduced in Plug-in Hybrid Electric Vehicles(PHEVs) mainly due to the design of these vehicles.

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Acceleration of the Precise Integration Method for Initial Value Problems Based on ACAP

Acceleration of the Precise Integration Method for Initial V...

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Cloud Computing, Big Data Applications and Software Engineering (CBASE), International conference on

作者： Yingchen Zhao Jixiao Wang Sheng Zhang Weisheng Zhang State Key Laboratory of Structural Analysis for Industrial Equipment Dalian University of Technology Dalian China Center for Nuclear Engineering Mechanics China Nuclear Power Engineering Co. Ltd Beijing China School of Mechanics and Aerospace Engineering Dalian University of Technology Dalian China

ISBN: (数字)9798331506582

ISBN: (纸本)9798331506599

This paper investigates the numerical implementation of solving initial value problems (IVPs) using the Precise Integration Method (PIM). For the solution of IVPs, PIM employs a recursive calculation based on matrix exponentiation, effectively avoiding the error accumulation often encountered in conventional numerical methods. The study focuses on the implementation of this method on a CPU, as well as its hardware-accelerated implementation on an Adaptive Compute Acceleration Platform (ACAP). By leveraging the powerful parallel processing capabilities of ACAP programmable logic (PL) and AI engines (AIE), the efficiency of complex numerical computations is significantly improved. Compared to traditional CPU platforms, ACAP demonstrates superior performance in large-scale computational tasks.

关键词： Cloud computing Parallel processing Big Data applications Computational efficiency logic Artificial intelligence Engines Software engineering

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Accelerating Image Processing Functions on ZYNQ-FPGA Using the Vitis Vision Library

Accelerating Image Processing Functions on ZYNQ-FPGA Using t...

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International conference on Advanced Electrical Engineering (ICAEE)

作者： Kamal Sehairi Thierry Bouwmans Laboratory of applied sciences and didactics Ecole Normale Supérieure de Laghouat Laghouat Algeria Lab. Mathématiques Image et Applications Université de La Rochelle La Rochelle France

ISBN: (数字)9798350349351

ISBN: (纸本)9798350349368

In the last decade, we have witnessed a high demand for high-resolution devices and screens. 4K and higher becomes a standard video definition, which requires special calculators such as DSPs, GPUs, TPUs, VPUs, and FPGAs. Among these accelerators, Xilinx has recently proposed a new system on chips -All programmable SOC, combining ARM processors and Artix-like mid-scale FPGA. Moreover, to facilitate implementation, Xilinx has upgraded their previous Vivado and Vivado HLS IDEs to the recent Vitis platform. In this work, we took advantage of these recent tools to design and implement higher-resolution image-processing applications on the PYNQ-Z1 board equipped with Zynq-7000 all-programmable SOC. We have accelerated OpenCV functions from the Vitis Vision Library by designing a processing system and programmable logic PS-PL scheme using Vitis HLS and Vivado. The co-design was ensured using the AXI interface to communicate between the PS and PL. Various image processing applications were designed and tested using Python in Jupiter Notebook. Results show that our co-design on the PYNQ-Z1 board accelerates edge detectors about 30× compared to the CPU implementation, while image filtering applications are accelerated by 10×. The project is available on GitHub. 1

关键词： Program processors Image edge detection Detectors Streaming media Libraries Software System-on-chip Field programmable gate arrays Standards Python

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A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA

A Novel Hardware Accelerator of NeRF Based on Xilinx UltraSc...

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International conference on Field programmable logic and Applications

作者： Baoze Zhao Wenjin Huang Yihua Huang School of Electronics and Information Technology Sun Yat-sen University Guangzhou China Southern Marine Science and Engineering Guangdong Laboratory Zhuhai China

Neural Radiance Fields (NeRF) has shown its superiority in various fields, including 3D reconstruction and inverse rendering. However, due to its high computational demands, NeRF typically requires implementation on high-performance GPUs, which is costly and power-intensive, thus limiting its applicability. Compared to GPUs, FPGAs offer a potential solution to implement NeRF at lower cost and power. However, FPGA-based NeRF designs are still rare. To address this issue, a novel hardware NeRF accelerator based on Xilinx UltraScale and UltraScale+ FPGA has been proposed. The proposed design is based on the Multiresolution Hash Encoding NeRF algorithm and comprises Feature Reader, Multilayer Perceptrons (MLP), and Volume Renderer. The Feature Reader and MLP calculate the coordinates and directions of the sampling points on the rays, which are then used to determine the colors and densities of these points. To prevent timing problems and routing congestion caused by high DSPs utilization, we use registers and cascade paths between DSPs to construct MACC matrices in MLP. The Volume Renderer processes these colors and densities to obtain the colors of rays. The proposed accelerator runs at 300MHz on Xilinx Alveo U250, achieving an average 1.60 × performance improvement compared to NVIDIA GTX 1080 Ti. Additionally, the accelerator has reduced energy consumption per image by an average of 5.21x and 4.64x compared to NVIDIA GTX 1080 Ti and NVIDIA RTX 3090, respectively.

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An infrared video image system design based on CameraLink

An infrared video image system design based on CameraLink

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International conference on Electronics and Information Technology (EIT)

作者： Weiwei Chen Lei Liu Rongguo Fu Huanan Zhang School of Electronic Engineering and Optoelectronic Technology Nanjing University of Science and Technology Nanjing China

ISBN: (数字)9798350369151

ISBN: (纸本)9798350369168

In order to address the limitations of the CameraLink interface infrared detector on the FPGA side, it was proposed that a wider clock frequency CameraLink decoding read-write display system be implemented. This would help to overcome the challenges posed by factors such as FPGA decoding clock frequency exceeding the generated clock jitter, line field signal instability, signal attenuation, and reflection. The hardware employs a decoding chip to complete the digital video image serial-to-parallel conversion of the CameraLink interface, subsequently outputting the LVCMOS signal. The software utilizes Xilinx IP and custom IP, in conjunction with an AXI4 bus interface, to implement FPGA control logic. Test results substantiate the feasibility of the design, demonstrating that the interface system is in accordance with the provisions of the AXI4 bus protocol, exhibiting high flexibility and application value.

关键词： Infrared detectors Protocols Cameras Software Decoding IP networks Field programmable gate arrays System analysis and design Standards Clocks

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FPGA-Based Efficient Implementation of CBNS Computational Circuits: A Modular Approach 3rd

FPGA-Based Efficient Implementation of CBNS Computational C...

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3rd International conference on Computational Advancement in Communication Circuits and Systems, ICCACCS 2020

作者： Mukherjee, Madhumita Sanyal, Salil Kumar Department of ETCE Jadavpur University Kolkata700032 India Department of ECE Narula Institute of Technology Agarpara Kolkata700109 India

ISBN: (纸本)9789811640346

Complex binary number system (CBNS) finds extensive applications in the faster computation of various digital signal processing (DSP) algorithms. In this paper, an attempt has been undertaken to develop various computational circuits based on CBNS for implementation in Spartan XC3S700A FPGA platform. The circuits have been designed following a modular approach. The designed modules involve simple logic gates leading ultimately to efficient implementation on FPGA. The codes for the modules have been developed using verilog hardware description language (HDL). Structural-level designs of nibble size CBNS adder, multiplier, and subtractor have been exclusively accomplished involving these modules. In the design of multiplier and subtractor, a new concept of sub-block has been introduced to efficiently utilize the limited input capability of the designed modules. The proposed design involves less hardware complexity, silicon area, and path delay compared to existing works. Simulation results and performance metrics for all the three CBNS circuits have been included. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Field programmable gate arrays (FPGA)

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Design of a Novel Electromechanical Flight Control Actuation System with Configurable Redundancy for UAVs 17th

Design of a Novel Electromechanical Flight Control Actuation...

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17th Chinese Intelligent Systems conference, CISC 2021

作者： Cao, Sijia Zhang, Hua Li, Chao Chen, Peng Jiang, Dikai Wu, Hao Zhao, Ruijing Lv, Wei Beijing Institute of Precision Mechatronics and Controls Beijing100076 China Laboratory of Aerospace Servo Actuation and Transmission Beijing100076 China The 3rd Military Representative Office of Rocket Force Armament Department in Beijing Beijing100076 China

ISBN: (纸本)9789811663277

As the demands of more electric or fully electrify in Unmanned Aerial Vehicle (UAV) flight control systems are emerging, a novel electromechanical flight control actuation system (FCAS) with the feature of configurable redundancy which is designed for a twin-engine long flight duration UAV is presented. The system is made up of 4 electrical controllers and 13 electromechanical actuators. The 4 controllers are powered by Digital Signal Processor (DSP) and Complex programmable logic Device (CPLD), each controller contains 4 power channels and can be utilized as either 4 independent channels or 2 two-redundancy channels according to the requirements of flight control configurations. The controllers are identical and replaceable with each other on board. For this design, the system layout and schematic are firstly presented. Then the detail design of the controller and the actuators are discussed, including the hardware and fault monitoring algorithm designs. Finally the ground test results and test considerations are addressed. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Controllers

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FPGA implementation of Hardware Accelerated 64-bit Floating Point Matrix-Multiplier for GNSS Data Processing

FPGA implementation of Hardware Accelerated 64-bit Floating ...

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International Symposium on Advanced Computing and Communication (ISACC)

作者： Durga Digdarsini Hem Raj Shau Nilay Jadav Guru Vignesh G SAC-ISRO Ahmedabad Gujarat EC CHARUSAT Anand Gujarat EE PSG College of Technology Coimbatore Tamilnadu

ISBN: (数字)9798331523893

ISBN: (纸本)9798331523909

This paper presents FPGA-based implementation of hardware accelerated matrix multiplier using High Level Synthesis (HLS) technique with a specific linkage to GNSS data processing. Matrix multiplication operation is a vital block for GNSS data processing. The multiplication of matrices of order greater than 10 consumes significant time in FPGA-based design. The total time for data processing need to be reduced for real-time scenario specially in case of space-based GNSS applications. For this purpose, HLS IP for matrix multiplication is developed to reduce the processing time substantially. In this work, 64-bit floating point data processing is achieved on 32–bit softcore processor, by design of control logic for seamless dataflow and synchronization between the HLS IP and other key modules in the FPGA. The design is tested in Xilinx Kintex Ultra FPGA-based KCU105 evaluation board. The hardware result for 40x40 matrices show that HLS-based approach achieves speedup factor up to 286 over standalone MicroBlaze softcore processor, this speedup is achieved at the expense of less than 3% percent of available major resources in the FPGA.

关键词： Couplings Global navigation satellite system Process control Data processing Hardware Real-time systems IP networks Synchronization logic Field programmable gate arrays

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SNAPE-FP: SqueezeNet CNN with Accelerated Pooling Layers Extension based on IEEE-754 Floating Point Implementation through SW/HW Partitioning On ZYNQ SoC 3

SNAPE-FP: SqueezeNet CNN with Accelerated Pooling Layers Ext...

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3rd Novel Intelligent and Leading Emerging Sciences conference, NILES 2021

作者： Abotaleb, Abdelrhman M. Ahmed, Mohab H. Fathi, Mazen A. Cairo University Electronics and Communications Engineering Department Giza12613 Egypt Cairo University Computer Engineering Department Giza12613 Egypt

ISBN: (纸本)9781665421577

It is clearly known that deep learning applications are enormously used in the image classification, object tracking and related image analysis techniques. But deep learning networks usually involve huge number of parameters that need to be extensively processed to produce the classification output, which also takes a considerable time. GPUs are exploited to do such huge parallel computations to be finished within acceptable time. Still GPUs consume huge power, so they are not suitable for embedded solutions, and also they are very expensive. In the current work, complete implementation of floating point based SqueezeNet convolutional neural network (CNN) is done on ZYNQ System-On-Chip (SoC) XC7020 via partitioning the implementation on both the software part (ARM) and the FPGA part (Artix-7), the acceleration is done via parallel implementations of average pool layer on up to 3 channels with speedup = 6.37 for the Max Pool layer accelerated single channel and 13.88 for the Average Pool layer accelerated 3 channels in parallel. The maximum power consumption equals 1.549 watt (only 0.136 watt for the static power consumption) and the remaining is the dynamic power consumption which is greatly less than the GPU power consumption (reaches 60 watt). © 2021 IEEE.

关键词： programmable logic controllers

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Research on Electrical Control and programmable Controller Based on Laser Tracking Measurement 3

Research on Electrical Control and Programmable Controller B...

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2020 3rd International Symposium on Power Electronics and Control Engineering, ISPECE 2020

作者： Xing, Guansheng Meng, Weichuan Qingdao University of Science and Technology Qingdao China School of Automation and Electrical Engineering Qingdao University of Science and Technology Qingdao China

Different production technology and process have different requirements for control circuit. However, no matter what kind of control circuit, it is composed of some basic control links. programmable controller is a common electronic data control program, which not only plays a lot of advantages in industrial control system, but also is more and more widely used in people's daily life. It is an essential basic equipment in industrial automation system at present. As a kind of high-precision three-coordinate measuring equipment, laser dynamic tracker can be used to measure the spatial position of various single parts and complete sets of equipment. This paper mainly introduces the application of laser tracking system in electrical control and programmable controller, and looks forward to the development prospect of laser tracking detection technology. © Published under licence by IOP Publishing Ltd.

关键词： programmable logic controllers

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