the ieee Std 1800-2005 SystemVerilog Standard added new implicit port instantiation enhancements that help accelerate toplevel composition of large ASIC & FPGA designs. this paper details the new .* and .name impl...
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ISBN:
(纸本)9781605581156
the ieee Std 1800-2005 SystemVerilog Standard added new implicit port instantiation enhancements that help accelerate toplevel composition of large ASIC & FPGA designs. this paper details the new .* and .name implicit port instantiation capabilities, the rules related to the use of these new enhancements, and how these enhancements offer concise RTL coding styles while enforcing stronger port-type checking.
Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up withthe imperfect flows typically used by their clients. Drawing on a car...
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ISBN:
(纸本)9781605581156
Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up withthe imperfect flows typically used by their clients. Drawing on a career's worth of mistakes knowledge, they present a set of coherent engineering principles for building a better flow infrastructure.
In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We...
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ISBN:
(纸本)9781605581156
In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
Handheld mobile terminals have developed from simple phones to devices featuring a wide variety of modem multimedia functions, being in fact multimedia computers. In today's mobile terminals, computational demand ...
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ISBN:
(纸本)9781605581156
Handheld mobile terminals have developed from simple phones to devices featuring a wide variety of modem multimedia functions, being in fact multimedia computers. In today's mobile terminals, computational demand is closes to that of personal desktop computers only a few years ago. All these new features need more power and bandwidth in interconnections. New innovations must be implemented in these devices with ever increasing speed.
the paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the p...
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ISBN:
(纸本)9781605581156
the paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. the platform has been implemented in a multimedia dual-core SOC design with little area overhead. Boththe benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.
Pattern matching relies on deterministic finite automata (DFA) to search for predefined patterns. While a bit-DFA method is recently proposed to exploit the parallelism in pattern matching, we identify its limitations...
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ISBN:
(纸本)9781605581156
Pattern matching relies on deterministic finite automata (DFA) to search for predefined patterns. While a bit-DFA method is recently proposed to exploit the parallelism in pattern matching, we identify its limitations and present two schemes, Label Translation Table (LTT) and CAM-based Lookup Table (CLT), to reduce the DFA memory size by 85%, and simplify the design by requiring only four processing elements of bit-DFA instead of thousands.
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional methods for addressing p...
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ISBN:
(纸本)9781605581156
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional methods for addressing performance and determinism become inadequate. this paper explores a new data cache design for use in modern high-performance embedded processors that will dynamically improve execution time, power efficiency, and determinism within the system. the simulation results show significant improvement in cache miss ratios and reduction in power consumption of approximately 30% and 15%, respectively.
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surfaces (GPRS) address this challenge by tra...
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ISBN:
(纸本)9781605581156
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surfaces (GPRS) address this challenge by transforming the optimization process from a lengthy series of detailed simulations into the tractable formulation and rapid evaluation of a predictive model. We validate GPRS methodology on realistic processor design spaces and compare it to recently proposed techniques for predictive microarchitectural design space exploration.
Error Detection FFs for Dynamic voltage Scaling (DVS) has been proposed. this technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. the error si...
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ISBN:
(纸本)9781605581156
Error Detection FFs for Dynamic voltage Scaling (DVS) has been proposed. this technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. the error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.
In this paper we present the design of a G.729a codec in a C-based design flow. the codec is used in VoIP applications for sending speech over internet protocol. We started from the standard reference C implementation...
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ISBN:
(纸本)9781605581156
In this paper we present the design of a G.729a codec in a C-based design flow. the codec is used in VoIP applications for sending speech over internet protocol. We started from the standard reference C implementation and generated several customized designs using the NISCT C-to-RTL toolset. Our final designs could run at very low clock frequencies (11 MHz for the decoder and 30 MHz for the coder) while meeting the timing requirements of the standard. We present these designs and the corresponding C-based design flow in this paper.
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