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检索条件"任意字段=4th Conference on Design and Process Integration for Microelectronic Manufacturing"

共 828 条记录，以下是21-30 订阅

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Application of design thinking in the Product Ideation Phase: Use of Agile Methodologies 4th

Application of Design Thinking in the Product Ideation Phase...

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4th International conference on Advanced Research in Technologies, Information, Innovation and Sustainability 2024, ARTIIS 2024

作者： Noversa, Ricardo Tereso, Anabela Sousa, Paulo Teixeira, Senhorinha Master’s in Engineering Project Management University of Minho Guimarães4804-533 Portugal ALGORITMI Research Centre/LASI Department of Production and Systems University of Minho Guimarães4710-057 Portugal

ISBN: (纸本)9783031832062

the transition to higher education presents challenges for incoming students. In a demanding academic environment, autonomy emphasizes fostering collaboration within the student community. this approach enhances interaction and integrates experienced students’ knowledge to support peers, aiming to improve academic performance. the study is centered on developing software prototypes for a digital platform to facilitate the intermediation of contacts among students, primarily for scheduling tutoring services. An Action Research strategy was employed, using focus group techniques to actively involve participants in the project. this method, supported by design thinking, utilized iterative phases that generated valuable insights, leading to the creation of several prototypes tailored to the real needs of users. this iterative process not only highlights the significance of each phase but also explores how they collectively enhance product software development, focusing on ideating and refining concepts based on the perspective of future users. the testing of these prototypes met user expectations, demonstrating the effectiveness of the design thinking approach. this contributed to satisfying user needs and promoting collaboration through interaction with the focus group. Moreover, adopting the Kanban project management method allowed for practical and efficient workflow management. Consequently, this article not only promotes methodologies that facilitate the ideation of a digital product designed to address a real-world need but also underscores how project management can be an integral ally in development, ensuring effective integration. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Project management

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Sequential PPC and process-window-aware mask layout synthesis

Sequential PPC and process-window-aware mask layout synthesi...

引用

4th conference on design and process integration for microelectronic manufacturing

作者： Sezginer, Apo Zach, Franz X. Yenikaya, Bayram Carrero, Jesus Huang, Hsu-Ting Invarium Inc San Jose CA 95110 USA

ISBN: (纸本)0819461997

We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. the cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. this increases immunity to bridging in low contrast areas.

关键词： Etching Photomasks process modeling Lithography Model-based design Data modeling Photoresist processing Tolerancing Image processing Semiconducting wafers

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OPC to improve lithographic process window

OPC to improve lithographic process window

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4th conference on design and process integration for microelectronic manufacturing

作者： Word, James Sakajiri, Kyohei Mentor Graph Corp Wilsonville OR 97070 USA

ISBN: (纸本)0819461997

Optical Proximity Correction (OPC) has become an indispensable tool used in deep sub-wavelength lithographic processes. OPC has been quite successful at reducing the linewidth dispersion across a product die, and also improving the overlapping process window of all printed features. this is achieved solely by biasing the mask features such that all print on target at the same dose. Recent advances in process window modeling, combined with highly customizable simulation and correction engines, have enabled process-aware OPC corrections. Building on these advances, the authors will describe a fast process Window OPC (PWOPC) technique. this technique results in layouts with reduced sensitivity to defocus variations, less susceptibility to bridging and pinching failures, and greater coverage of over/underlying features (such as contact coverage by metal).

关键词： OPC DOF RET DFM process window

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Layout verification and optimization based on flexible design rules

Layout verification and optimization based on flexible desig...

引用

4th conference on design and process integration for microelectronic manufacturing

作者： Yang, Jie Capodieci, Luigi Sylvester, Dennis Adv Micro Devices Inc Sunnyvale CA 94085 USA Univ Michigan EECS Dept Ann Arbor MI 48109 USA

ISBN: (纸本)0819461997

A methodology for layout verification and optimization based on flexible design rules is provided. this methodology is based on image parameter determined flexible design rules (FDRs), in contrast with restrictive design rules (RDRs), and enables fine-grained optimization of designs in the yield-performance space. Conventional design rules are developed based on experimental data obtained from design, fabrication and measurements of a set of test structures. they are generated at, early stage of a process development and used as guidelines for later IC layouts. these design rules (DRs) serve to guarantee a high functional yield of the fabricated design. Since small areas are preferred in integrated circuit designs due to their corresponding high speed and lower cost, most design rules focus on minimum resolvable dimensions.

关键词： design rule manual resolution enhancement techniques optical proximity correction design for manufacturing restricted design rules

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Silicon IP reuse standards for design for manufacturability

Silicon IP reuse standards for design for manufacturability

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4th conference on design and process integration for microelectronic manufacturing

作者： Carballo, Juan Antonio Sundareswaran, Savithri IBM Almaden Res Lab San Jose CA 95123 USA Freescale Semicond Austin TX USA

ISBN: (纸本)0819461997

design for Manufacturability (DFM) has become a major semiconductor topic that spans various issues, including issues related to lithography hardware limitations, and issues related to variability. there is, however, an issue that crosses multiple DFM domains: the need to reuse designed Silicon IP blocks or "cores" across various manufacturing processes. Unfortunately, there are no standards to facilitate the reuse of circuit blocks while addressing the lithography- and variability-related issues. Specifically, there is no clear definition for a user of a core to evaluate "manufacturability" of a core for a set of foundry processes. We present a quantitative DFM standard for Silicon IP reuse, which addresses this problem. this work was done in conjunction with VSIA's DFM team.

关键词： design IP manufacturability standards reuse

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the use of process models to enhance device performance through semiconductor design

The use of process models to enhance device performance thro...

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4th conference on design and process integration for microelectronic manufacturing

作者： Melvin, Lawrence S., III Zhang, Daniel Synopsys Inc 2025 NW Cornelius Pass Rd Hillsboro OR 97124 USA

ISBN: (纸本)0819461997

As semiconductor manufacturing nodes march towards increasingly aggressive process nodes, the features that can be manufactured on a silicon wafer are becoming more and more constrained. these constraints are arising from the need for manufacturing process margin, the result of which is improved yields and wafer throughput. For less aggressive process nodes, these constraints have been transferred between the design and manufacturing communities using tables of design rules. However, as process nodes march forward, these are rules are getting complex and unmanageable. A better methodology to communicate design rules is to build a model of the manufacturing process for use by the design team. this model can then be used to analyze a piece of layout for manufacturing robustness, and allow the design to make informed layout revisions. design rules encompass effects due to many manufacturing processes including exposure, registration. etch, reticle construction, electro migration, etc. In order to create useful design rules, all of these processes must be understood and combined into a set of process rules. In order to reduce the complexity of the design rules table, a process model may be applied in complex pattern configurations. this study will seek to understand the definition of complex configurations for photolithography design rules, and it will attempt to demonstrate the usefulness of model-based design rules.

关键词： design Rule Check process model

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A genuine design manufacturability check for designers

A genuine design manufacturability check for designers

引用

4th conference on design and process integration for microelectronic manufacturing

作者： Hurat, Philippe Cote, Michel Tsai, Chi-Ming Brandenburg, Joe Clear Shape Technol Inc 440 N Wolfe Rd Sunnyvale CA 94085 USA

ISBN: (纸本)0819461997

the design of integrated circuits (ICs) has been made possible by a simple contract between design and manufacturing: manufacturing teams encapsulated their process capabilities into a set of design rules such as minimum width and spacing or overlap for each layer, and designers complied with these design rules to get a manufacturable IC. However, since the advent of 90nm technology, designers have to play by the new rules of sub-90nm technologies. the simple design rules have evolved into extremely complex, context-dependent rules. Minimum design rules have been augmented with many levels of yield-driven recommended guidelines. One of the main drivers behind these complex rules is the increase in optical proximity effects that are directly impacting systematic and parametric yields for sub-90nm designs. the design's sensitivity to optical proximity effects increases as features get smaller, however design engineers do not have visibility into the manufacturability of these features.

关键词： manufacturing design for manufacturability Resolution enhancement technologies Integrated circuit design design for manufacturing Optical proximity correction Photomasks Optics manufacturing Data modeling Lithography

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DFM requirements and solution roadmaps: the multi-layer approach

DFM requirements and solution roadmaps: The multi-layer appr...

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4th conference on design and process integration for microelectronic manufacturing

作者： Carballo, Juan Antonio Nassif, Sani IBM Almaden Res Lab San Jose CA 95123 USA IBM Austin Res Lab Austin TX 78758 USA

ISBN: (纸本)0819461997

design For Manufacturability (DFM) has emerged as a major driver as the semiconductor industry continues on its historic scaling trend. the International Technology Roadmap for Semiconductors (ITRS) design Group has engaged in a major overhaul of the design Technology Roadmap, including a completely new section focused on DFM. As part of that overhaul, it was observed that quantifying and road-mapping DFM requires effective yet simple models that can relate broad technology characteristics to specific circuit performances such as delay and power. In this article, we discuss the general topic of DFM roadmaps, and show a simple performance model built upon a canonical circuit and analytical solution that is parameterized such that it can address the DFM roadmap problem. We also show that for important model parameters such as threshold voltage, it may be necessary to apportion the various spaces of variability.

关键词： semiconductor roadmap manufacturing variability electronic design

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Annotated layout optimization

Annotated layout optimization

引用

4th conference on design and process integration for microelectronic manufacturing

作者： thiele, Joerg Koehle, Roderick Infineon Technol AG D-81726 Munich Germany

ISBN: (纸本)0819461997

the annotation of electrical information or constraints is a well established method to transfer information on design intent from the electrical to the physical designer. In this paper, we will discuss the possibility to extend the concept of annotation as vehicle to hand over critical information from the physical designer to the resolution enhancement technique (RET) engineer. Opportunities and implications to extend the existing optical proximity correction (OPC) methods from the current stage of "just print the layout on wafer" towards new approaches where the layout can be optimized during the RET/OPC step based on designers input are discussed. In addition, the benefit of using process variation information for this layout optimization will be compared to a conventional OPC approach that just tries to realize an overlapping process window at one point of the process window. the power of a combination of both approaches will be shown, based on a small test case. the target of this work is to motivate further research and development in this direction to enhance the current OPC/RET capabilities towards a more integrated solution enabling annotated layout optimization as link between design and manufacturing.

关键词： design for manufacturability DtM optical proximity correction OPC resolution enhancement techniques RET

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A heuristic method for statistical digital circuit sizing

A heuristic method for statistical digital circuit sizing

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4th conference on design and process integration for microelectronic manufacturing

作者： Boyd, Stephen Kim, Seting-Jean Patil, Dinesh Horowitz, Mark Stanford Univ Dept Elect Engn Informat Syst Lab Stanford CA 94305 USA

ISBN: (纸本)0819461997

In this paper we give a brief overview of a heuristic method for approximately solving a statistical digital circuit sizing problem, by reducing it to a related deterministic sizing problem that includes extra margins in each of the gate delays to account for the variation. Since the method is based on solving a deterministic sizing problem, it readily handles large-scale problems. Numerical experiments show that the resulting designs are often substantiallv better than one in which the variation in delay is ignored, and often quite close to the global optimum. Moreover, the designs seem to be good despite the simplicity of the statistical model (which ignores gate distribution shape, correlations, and so on). We illustrate the method on a 32-bit Ladner-Fischer adder, with a simple resistor-capacitor (RC) delay model, and a Pelgrom model of delay variation.

关键词： design for manufacturing design for yield statistical circuit sizing

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