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4th conference on design and process integration for microelectronic manufacturing

作者： Hong, Le Brist, Travis LaCour, Pat Sturtevant, John Niehoff, Martin Niedermaier, Philipp Mentor Graph Corp Wilsonville OR 97070 USA Mentor Graph Corp Munich Germany Infineon Technol AG Munich Germany

ISBN: (纸本)0819461997

the latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. this coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. this paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. the impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.

关键词： OPC ACLV CD variation gate verification

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design-friendly DFM rule

Design-friendly DFM rule

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4th conference on design and process integration for microelectronic manufacturing

作者： Osawa, Morimi Minami, Takayoshi Futatsuya, Hiroki Asai, Satoru Fujitsu Ltd Akiruno Technol Ctr 50 Fuchigami Tokyo 1970833 Japan

ISBN: (纸本)0819461997

We proposed a design-friendly DFM rule intended to improve circuit performance. To reduce variations in the gate length, we applied active usage of preferred gate spaces and optimized the lithographic conditions. We selected the spaces to take into account the layouts that are used most frequently in actual design, so that many designers who are worrying about chip area and performance can follow the rule. the effect of our method was evaluated for 65-nm node technology. From the viewpoint of gate length, parallel usage of design following the rule and optimization lead to an 8% decrease in variation, and a 38% decrease in the mean difference from the targeted gate length. We also evaluated the effect on delays using an accurate method that can treat both statistical and systematic variation. the difference in the average delay from the tar targeted value was reduced from about 1% to less than 0.1%, and a 10% improvement in delay variation was observed.

关键词： DFM preferred rule recommended rule litho-friendly design standard cell gate length variation

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RF integrated systems

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microelectronic ENGINEERING 2000年第1-2期54卷 103-111页

作者： Belot, D STMicroelect F-38926 Crolles France

this article will detail the advantages and the draw back of the monochip approach for the system integration, the process selection (CMOS or BiCMOS), and the needed knowledge to perform a successful design. A BICMOS monochip, RF to digital base band on DCS1800 standard will be presented. this circuit has been designed in order to underline the substrate coupling effects. Linked to this design, a substrate coupling study will be developed. A low cost CMOS zero IF Bluetooth RF front end design will be detailed, this approach is defined in order to integrate the global RF and Base Band functions in a monochip.

关键词： radiofrequency coupling effect BiCMOS Systems integration INTEGRATED SHIP CONTROL Baseband RETREAT MINING

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Reducing DfM to practice: the lithography manufacturability assessor - art. no. 61560K

Reducing DfM to practice: the lithography manufacturability ...

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4th conference on design and process integration for microelectronic manufacturing

作者： Liebmann, Lars Mansfield, Scott Han, Geng Culp, James Hibbeler, Jason Tsai, Roger IBM Corp. (United States)

ISBN: (纸本)0819461997

the need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. the importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. the need for extensive experimental calibration and improved simulation accuracy is also highlighted.

关键词： design for manufacturability (DfM) resolution enhancement techniques (RET) critical area analysis (CAA) quantifying manufacturability lithography manufacturability assessor

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Challenges and solutions for trench lithography beyond 65nm node

Challenges and solutions for trench lithography beyond 65nm ...

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4th conference on design and process integration for microelectronic manufacturing

作者： Lu, Zhijian (George) Ho, Chi-Chien Mason, Mark Anderson, Andrew Mckee, Randy Jackson, Ricky Zhu, Cynthia Terry, Mark 13560 North Cent Expressway Dallas TX 75243 USA

ISBN: (纸本)0819461997

Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. these systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. these defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. this paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "thin-Line," and "Bowling Pin" defects during 65nm product development at TI. through case studies, we demonstrate how to successfully provide DFM (design for manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.

关键词： model-based OPC systematic defects process rules 65nm node DFM dummy metal fill design rules full-chip simulation BEOL

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Experimental verification of improved printability for litho-driven designs

Experimental verification of improved printability for litho...

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4th conference on design and process integration for microelectronic manufacturing

作者： van Wingerden, Johannes Le Cam, Laurent Wientjes, Rene Benndorf, Michael Trouiller, Yorick Belledent, Jerome Morton, Rob Aksenov, Yuri Philips Res Europe B-3001 Leuven Belgium Philips Semicond Crolles2Alliance F-38926 Crolles France Philips Semicond CTO NL-6534 AE Nijmegen Netherlands CEA Crolles2Alliance LETI F-38926 Crolles France

ISBN: (纸本)0819461997

the continued downscaling of the feature sizes and pitches for each new process generation increases the challenges for obtaining sufficient process control. As the dimensions approach the limits of the lithographic capabilities, new solutions for improving the printability are required. Including the design into the optimization process significantly improves the printability. the use of litho-driven designs becomes increasingly important towards the 45 nm node. the litho-driven design is applied to the active, pate, contact and metal layers. It has been shown previously, that the impact on the chip area is negligible. Simulations have indicated a significant improvement in controlling the critical dimensions of the gate layer. In this paper, we present our first results of an experimental validation of litho-driven designs printed oil an immersion scanner. In our design we use a fixed pitch approach that allows to match the illumination conditions to those for the memory structures. the impact on the chip area and on the CD control will be discussed. the resulting improvement in CD control is demonstrated experimentally by comparing the experimental results of litho-driven and standard designs. A comparison with simulations will be presented.

关键词： Optical Lithography design for manufacturing Litho Driven design Fixed Pitch design low k(1)

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Call for an industry standard for pattern transfer models for usage in OPC and design for manufacturability

Call for an industry standard for pattern transfer models fo...

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4th conference on design and process integration for microelectronic manufacturing

作者： Roessler, thomas Grimm, Wolfgang thiele, Joerg Infineon Technol AG POB 800949 D-81609 Munich Germany

ISBN: (纸本)0819461997

Lately, "design for Manufacturability" (DFM) can be found in almost any self-respecting EDA vendor's top-five list of most critical and urgent strategic topics. While the envisioned DFM activities cover a broad spectrum of topics, the exact definition of DFM continues to evade capture [1]. However, it appears self-evident that an important portion of DFM hinges upon the availability of models accurately describing the pattern transfer from the layout to the wafer, here called "pattern transfer models" (PTMs). In combination with a suitable design environment, PTMs will allow physical designers to optimize their layout, thus ensuring the structural integrity over the process window upon transfer to the wafer. In this paper, we argue that PTMs have an importance comparable to that of the "electrical device models" (EDMs) widely used for circuit simulation. We point out some striking analogies between PTMs and EDMs, as far as the basic concepts and use models are concerned. Furthermore, we highlight the significant differences in the EDA landscapes for both model types, most importantly the fact that an industry standard only exists for EDMs. Based on the consequences for EDA vendors and users, as well as manufacturing cooperations that derive from this situation, we formulate the call for an industry standard for PTMs for usage in "Optical Proximity Correction" (OPC) and DFM.

关键词： OPC lithography DFM RET yield design models pattern transfer simulation standardization

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From poly line to transistor: Building BSIM models for non-rectangular transistors

From poly line to transistor: Building BSIM models for non-r...

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4th conference on design and process integration for microelectronic manufacturing

作者： Poppe, Wojtek J. Capodieci, Luigi Wu, Joanne Neureuther, Andrew Univ Calif Berkeley ERL Berkeley CA 94720 USA AMD Sunnyvale CA 94085 USA

ISBN: (纸本)0819461997

Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. the transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. this is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. there have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. this paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.

关键词： Transistors Critical dimension metrology Device simulation Optical proximity correction Capacitance manufacturing design for manufacturability Ions Oscillators design for manufacturing

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Platform for collaborative DFM

Platform for collaborative DFM

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4th conference on design and process integration for microelectronic manufacturing

作者： Poppe, Wjtek J. Capodieci, Luigi Neureuther, Andrew Univ Calif Berkeley ERL Berkeley CA 94720 USA AMD Sunnyvale CA 94085 USA

ISBN: (纸本)0819461997

A process/Device/design framework called the Parametric Yield Simulator is proposed for predicting circuit variability based on circuit design and a set of characterized sources of variation. In this simulator, the aerial image of a layout is simulated across a predefined process window and resulting non-idealities in geometrical features are communicated through to circuit simulators, where circuit robustness and yield can be evaluate in terms of leakage and delay variability. the purpose of this simulator is to identify problem areas in a layout and quantify them in terms of delay and leakage in a manner in which designers and process engineers can collaborate together on an optimal solution to the problem. the Parametric Yield Simulator will serve as a launch pad for collaborative efforts between groups in different disciplines that are looking at variability and yield. Universities such as Berkeley offer a great advantage in exploring innovative approaches as different centers of key expertise exist under one roof For example a complementary set of characterization and validation experiments has also been designed and in a collaborative study is being executed at Cypress semiconductor on a 65nm NMOS process flow. this unique opportunity of having access to a cutting edge process flow with relatively high transparency has led to a new set of experiments with contributions from six different students in circuit design, process engineering, and device physics. Collaborative efforts with the device group have also led to a new electrical linewidth metrology methodology using enhanced transistors that could prove useful for process characterization.

关键词： Transistors Critical dimension metrology Device simulation design for manufacturing Semiconductors Optical proximity correction Photomasks Metrology Image processing Physics

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Towards DFM : process worthy design and OPC through verification method using MEEF, TF-MEEF and MTT

Towards DFM : Process worthy design and OPC through verifica...

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4th conference on design and process integration for microelectronic manufacturing

作者： Kim, In-Sung Suh, Sungsoo Jung, Sunggon Lee, Eunmi Kang, Young-Seog Lee, Sukjoo Woo, Sang-Gyun Cho, Hanku Samsung Elect Co LTD Semicond R&D Yongin 449711 Gyeonggi Do South Korea

ISBN: (纸本)0819461997

design for manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designer's intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographer's understanding of DIM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy. In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. the DFM can be viewed as flattening the TF-MEEF across the design.

关键词： DFM OPC design verification MEEF TF-MEEF MTT photomask

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