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Foxes and chickens: An android game

Foxes and chickens: An android game

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25th International conference on Computer Applications in Industry and Engineering, CAINE 2012 and the 4th International symposium on Sensor Network and Application, SNA 2012

作者： Martinez, Justin R. Luo, Wenbin Engineering Department St. Mary's University San Antonio TX 78228 United States

ISBN: (纸本)9781880843888

In this paper, we present the design, implementation, and testing of an Android game, called Foxes and Chickens. It was developed for mobile devices with the Android mobile operating system. the Foxes and Chickens game itself has origins in South America, where it is very popular in some countries. However, to the best of our knowledge, no digital version of the game was available for mass consumption. Our research seeks to remedy this vacancy with the goal of adding values and enjoyment to users of the Android mobile devices. After going through strict software engineering processes of specification, design, coding, and testing, we successfully developed the game, as shown at the following link: http://***/watchv=xeXYiR3Qwio. the game Foxes and Chickens is available for download from the Android market for anyone with an Android powered device. It has been tested for compatibility on the following mobile devices: T-Mobile's G1, HTC MyTouch, and Verizon's Motorola Droid. It should run on other compatible Android handsets as well. Copyright © 2012 by International Society of Computers and their Applications (ISCA).

关键词： Android (operating system)

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Energy-Delay Trade-Offs in Instruction Register File design 4

Energy-Delay Trade-Offs in Instruction Register File Design

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4th IEEE Nordic Circuits and systems conference (NORCAS) / NORCHIP and International symposium of system-on-Chip (SoC)

作者： Multanen, Joonas Kultala, Heikki Jaaskelainen, Pekka Tampere Univ Technol Tampere Finland

ISBN: (纸本)9781538676561

In order to decrease latency and energy consumption, processors use hierarchical memory systems to store temporally and spatially related instructions close to the core. Instruction register file (IRF) is an energy-efficient solution for the lowest level in the instruction memory hierarcy. Being compiler-controlled, it removes the area and energy overheads involved in cache tag checking and adds flexibility in the separation of the instruction fetch and execution. In this paper, we systematically evaluate for the first time the effect of three IRF design variations on energy and delay against an unoptimized baseline IRF. Having instruction fetch and decode with IRF in the same pipeline stage allows minimal delay branching, but results in low operating clock frequency and impaired energy delay product compared to splitting them into two stages. Assuring instruction presence in IRF before execution with software reduces the area and increases maximum clock frequency compared to assurance with hardware, but requires compiler analysis. With a proposed compiler-analyzed instruction placement and co-designed hardware implementation, energy consumption with the best IRF variant is reduced by 9% on average with EEMBC Coremark and CHStone benchmaks. the energy delay product is improved by 23% when compared to the baseline IRF approach.

关键词： Registers Program processors Delays Clocks Hardware Task analysis

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aDFS: An Almost Depth-First-Search Distributed Graph-Querying system

aDFS: An Almost Depth-First-Search Distributed Graph-Queryin...

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USENIX Annual Technical conference / 15th USENIX symposium on operating systems design and implementation (osdi)

作者： Trigonakis, Vasileios Lozi, Jean-Pierre Faltin, Tomas Roth, Nicholas P. Psaroudakis, Iraklis Delamare, Arnaud Haprian, Vlad Iorgulescu, Calin Koupy, Petr Lee, Jinsoo Hong, Sungpack Chafi, Hassan Oracle Labs Santa Clara CA 95054 USA Charles Univ Prague Prague Czech Republic KUNGFU AI Austin TX USA

ISBN: (纸本)9781939133236

Graph processing is an invaluable tool for data analytics. In particular, pattern-matching queries enable flexible graph exploration and analysis, similar to what SQL provides for relational databases. Graph queries focus on following connections in the data;they are a challenging workload because even seemingly trivial queries can easily produce billions of intermediate results and irregular data access patterns. In this paper, we introduce aDFS: A distributed graphquerying system that can process practically any query fully in memory, while maintaining bounded runtime memory consumption. To achieve this behavior, aDFS relies on (i) almost depth-first (aDFS) graph exploration with some breadth-first characteristics for performance, and (ii) non-blocking dispatching of intermediate results to remote edges. We evaluate aDFS against state-of-the-art graph-querying (Neo4J and GraphFrames for Apache Spark), graph-mining (G-Miner, Fractal, and Peregrine), as well as dataflow joins (BiGJoin), and show that aDFS significantly outperforms prior work on a diverse selection of workloads.

关键词： Pattern matching

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design and implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture 4

Design and Implementation of Multi-Purpose DCT/DST-Specific ...

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4th IEEE Nordic Circuits and systems conference (NORCAS) / NORCHIP and International symposium of system-on-Chip (SoC)

作者： Nouri, Sajjad Ghaznavi-Youvalari, Ramin Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn Tampere Finland Nokia Technol Espoo Finland

ISBN: (纸本)9781538676561

this paper presents the implementation of various sizes of Discrete Cosine transform (DCT) and Discrete Sine Transform (DST) dedicated for High Efficiency Video Coding (HEVC) standard by using template-based Coarse-Grained Reconfigurable Arrays (CGRAs) as accelerators on Heterogeneous Accelerator-Rich Platform (HARP). the proposal makes multipurpose DCT/DST specific accelerators in such a way that final architecture consists of 4/8/16/32-point DCT and 4-point DST. the accelerators are primarily designed by crafting template-based CGRA devices at different dimensions and then arranging them on a Network-on-Chip platform along with a few RISC cores. In this research work, the performance of each DCT/DST-specific accelerator, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Conducted experiments show that 4-point DCT and 4-point DST can be implemented completely in 54 and 56 clock cycles, respectively, while for 8/16/32-point DCT, 67, 179 and 354 clock cycles are required, respectively. the achieved total power dissipation and energy consumption based on post placement and routing information are equal to 4.1 W and 10.87 mu J, respectively with 256 instantiated Processing Elements (PEs) at 200.0 MHz operating frequency. It resulted to a performance of 51.2 Giga Operations Per Second (GOPS) and 12 MOPS/mW as an architectural constant for the HARP template on 28 nm Altera Stratix-V chip. the proposed architecture is able to sustain Full HD 1080p format at 30 fps on FPGA.

关键词： Reconfigurable CGRA Network-on-Chip Heterogeneous Accelerator Multicore DCT DST HEVC

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design and implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture 4

Design and Implementation of 2D IDCT/IDST-Specific Accelerat...

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4th IEEE Nordic Circuits and systems conference (NORCAS) / NORCHIP and International symposium of system-on-Chip (SoC)

作者： Pourabed, Mohammad Ali Nouri, Sajjad Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn POB 553 FI-33101 Tampere Finland

ISBN: (纸本)9781538676561

the paper talks about how to implement different sizes of Inverse Discrete Cosine Transform (IDCT) as well as Inverse Discrete Sine transform (IDST) that are dedicated on High Efficiency Video Coding (HEVC) standard through employing Coarse-Grained Reconfigurable Arrays (CGRAs) as a template-based accelerators on Heterogeneous Accelerator-Rich Platform (HARP). the proposal designs multi-purpose IDCT/IDST-based accelerators in a manner that the final architecture is made up of 4-point IDST and 4/8-point IDCT. the designing of the accelerators is done by creating template-based CGRA devices at various dimensions after which they are arranged in a sequential manner over a structure that is Network-on-Chip (NoC) based accompanied by a number of RISC cores. the research records the IDCT/IDST-specific accelerator performance, the entire platform's performance, as well as the traffic of the NoC with regard to the total number of clock cycles made as well as several other high-level metrics of performance. the experiments that were conducted found that 4-point IDCT and 4-point IDST can be totally implemented in 56 clock cycles. For 8-point IDCT, the clock cycles required are 64. the total power dissipation, as well as energy consumption centred on information on routing and post placement, are all equal to 4.03 mW and 1.76 mu J for 4-point IDCT/IDST and 3.06 mu J for 8-point IDCT, respectively. Furthermore, the use of 256 instantiated Processing Elements (PEs) at an operating frequency of 200.0 MHz results to a 51.2 Giga Operations Per Second (GOPS) performance and 0.012 GOPS/mW architectural constant for the HARP model on the 28 nm Altera Stratix-V chip. the architecture under the proposal is capable of fully sustaining a format of Full HD 1080P at 30 fps on FPGA.

关键词： IDCT IDST HEVC HARP CGRA Multicore NoC RISC FPGA

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system support for bandwidth management and content adaptation in internet applications 00

System support for bandwidth management and content adaptati...

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Proceedings of the 4th conference on symposium on operating system design & implementation - Volume 4

作者： David Andersen Deepak Bansal Dorothy Curtis Srinivasan Seshan Hari Balakrishnan M.I.T. Laboratory for Computer Science Cambridge MA Carnegie Mellon University Pittsburgh PA and M.I.T. Laboratory for Computer Science Cambridge MA

this paper describes the implementation and evaluation of an operating system module, the Congestion Manager (CM), which provides integrated network flow management and exports a convenient programming interface that allows applications to be notified of, and adapt to, changing network conditions. We describe the API by which applications interface with the CM, and the architectural considerations that factored into the design. To evaluate the architecture and API, we describe our implementations of TCP; a streaming layered audio/video application; and an interactive audio application using the CM, and show that they achieve adaptive behavior without incurring much end-system overhead. All flows including TCP benefit from the sharing of congestion information, and applications are able to incorporate new functionality such as congestion control and adaptive behavior.

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End-to-end authorization 00

End-to-end authorization

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Proceedings of the 4th conference on symposium on operating system design & implementation - Volume 4

作者： Jon Howell David Kotz Consystant Design Technologies Department of Computer Science Dartmouth College

Many boundaries impede the flow of authorization information, forcing applications that span those boundaries into hop-by-hop approaches to authorization. We present a unified approach to authorization. Our approach allows applications that span administrative, network, abstraction, and protocol boundaries to understand the end-to-end authority that justifies any given request. the resulting distributed systems are more secure and easier to *** describe boundaries that can interfere with end-to-end authorization, and outline our unified approach. We describe the system we built and the applications we adapted to use our unified authorization system, and measure its costs. We conclude that our system is a practical approach to the desirable goal of end-to-end authorization.

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How to build a trusted database system on untrusted storage 00

How to build a trusted database system on untrusted storage

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Proceedings of the 4th conference on symposium on operating system design & implementation - Volume 4

作者： Umesh Maheshwari Radek Vingralek William Shapiro STAR Lab InterTrust Technologies Corporation Santa Clara CA

Some emerging applications require programs to maintain sensitive state on untrusted hosts. this paper presents the architecture and implementation of a trusted database system, TDB, which leverages a small amount of trusted storage to protect a scalable amount of untrusted storage. the database is encrypted and validated against a collision-resistant hash kept in trusted storage, so untrusted programs cannot read the database or modify it undetectably. TDB integrates encryption and hashing with a low-level data model, which protects data and metadata uniformly, unlike systems built on top of a conventional database system. the implementation exploits synergies between hashing and log-structured storage. Preliminary performance results show that TDB outperforms an off-the-shelf embedded database system, thus supporting the suitability of the TDB architecture.

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design and evaluation of a continuous consistency model for replicated services 00

Design and evaluation of a continuous consistency model for ...

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Proceedings of the 4th conference on symposium on operating system design & implementation - Volume 4

作者： Haifeng Yu Amin Vahdat Computer Science Department Duke University Durham NC

the tradeoffs between consistency, performance, and availability are well understood. Traditionally, however, designers of replicated systems have been forced to choose from either strong consistency guarantees or none at all. this paper explores the semantic space between traditional strong and optimistic consistency models for replicated services. We argue that an important class of applications can tolerate relaxed consistency, but benefit from bounding the maximum rate of inconsistent access in an application-specific manner. thus, we develop a set of metrics, Numerical Error, Order Error, and Staleness, to capture the consistency spectrum. We then present the design and implementation of TACT, a middleware layer that enforces arbitrary consistency bounds among replicas using these metrics. Finally, we show that three replicated applications demonstrate significant semantic and performance benefits from using our framework.

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Proactive recovery in a Byzantine-fault-tolerant system 00

Proactive recovery in a Byzantine-fault-tolerant system

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Proceedings of the 4th conference on symposium on operating system design & implementation - Volume 4

作者： Miguel Castro Barbara Liskov Laboratory for Computer Science Massachusetts Institute of Technology Cambridge MA

this paper describes an asynchronous state-machine replication system that tolerates Byzantine faults, which can be caused by malicious attacks or software errors. Our system is the first to recover Byzantine-faulty replicas proactively and it performs well because it uses symmetric rather than public-key cryptography for authentication. the recovery mechanism allows us to tolerate any number of faults over the lifetime of the system provided fewer than 1/3 of the replicas become faulty within a window of vulnerability that is small under normal conditions. the window may increase under a denial-of-service attack but we can detect and respond to such attacks. the paper presents results of experiments showing that overall performance is good and that even a small window of vulnerability has little impact on service latency.

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