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检索条件"任意字段=4th IEEE International Conference on Field Programmable Technology"

共 7617 条记录，以下是1-10 订阅

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A Fast Frequency Measurement Circuit With Low Latency Developed Using FPGA 4

A Fast Frequency Measurement Circuit With Low Latency Develo...

引用

4th international Symposium on Instrumentation, Control, Artificial Intelligence, and Robotics, ICA-SYMP 2025

作者： Sharani, Sohoda Sri Hsieh, Kuan-Ping Lu, Yun-Chih Chen, Jau-Horng Chen, Yi-Jan Emery Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan National Taiwan University Department of Engineering Science and Ocean Engineering Taipei Taiwan Graduate Institute of Electronics Engineering Graduate Institute of Communication Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798331505400

this paper presents the design and challenges of the statistical frequency measurement technique, which can be implemented using a field-programmable gate array (FPGA) board. the frequency measurement range is from 200 MHz to 715 MHz, with errors of less than 500 kHz. the latency of the first measurement result is only 360 ns, and consecutive measurement results of the same frequency signal can be obtained every 20 ns. Higher frequency accuracy can be effectuated by increasing the measurement latency. © 2025 ieee.

关键词： field programmable gate arrays (FPGA)

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Low field MRI Image Synthesis 4

Low Field MRI Image Synthesis

引用

4th ieee international conference on Artificial Intelligence in Cybersecurity, ICAIC 2025

作者： Wang, Kun Jin, Aobo Guo, Hongchun Wan, Yun Deng, Qixin Chu, Wenhui Raval, Maulin Gohel, Hardik University of Houston Computer Science Houston United States University of Houston Victoria Computer Science Victoria United States Chaoyang Engineering Technology School Basic English Chaoyang China Mathematics and Computer Science Wabash College Crawfordsville United States Computer Science Texas A&M University College Station United States

ISBN: (纸本)9798331518882

Low-field MRI image creation attracts attention because it is critical for advancing medical imaging research. Synthesized low-field MRI images can be automatically paired with relative high-field MRI images to form the dataset to train super-resolution deep learning models. In this work, we provide a detailed comparison of two different approaches to low-field MRI image synthesis, each aimed at simulating the various imaging properties of low-field systems. We propose a series of quantitative and qualitative metrics to evaluate the performance of each method, assessing its ability to replicate critical attributes such as noise levels, spatial resolution, dynamic range, and preservation of anatomical structures. through the analysis of these variables, we want to highlight the merits and drawbacks of each technique and provide valuable insights into their appropriateness for various clinical and research applications. this review aims to offer suggestions for developing more reliable and accurate low-field MRI synthesis procedures, particularly in resource-constrained contexts where high-field MRI systems may be inaccessible. © 2025 ieee.

关键词： Magnetic resonance imaging

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A Wide Range and Highly Linear ISFET Readout Circuit 4

A Wide Range and Highly Linear ISFET Readout Circuit

引用

4th international conference on Robotics, Electrical and Signal Processing Techniques, ICREST 2025

作者： Saywan, Niramol Yodtean, Apiradee Silapan, Phamorn Jewajinda, Yutana Faculty of Engineering and Industrial Technology Department of Electrical Engineering Nakhonpathom Thailand Pathum Thani Thailand

ISBN: (纸本)9798331530938

the article introduces a highly linear readout circuit for ion-sensitive field-effect transistors (ISFET) developed in 0.8 μ μm CMOS technology. the proposed circuit comprises only eight transistors and a resistor, providing wide input ranges with high linearity. Simulation results from the LTSpice application indicate that the proposed circuit can function across a wide input range of 0.6-3.1 V. It exhibits a sensitivity of 38.3 mV/pH and a linearity of 0.9994 when simulated with a power supply of 3.3 volts. the power consumption rate is 34.42 μ W. © 2025 ieee.

关键词： Ion sensitive field effect transistors

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Research on the Collaborative Mechanism of P4Runtime and SAI in White Box Switches Based on the SONiC System 5

Research on the Collaborative Mechanism of P4Runtime and SAI...

引用

5th ieee international conference on Power, Electronics and Computer Applications, ICPECA 2025

作者： Pan, Zhuyu Wang, Hongchao Yan, Chen Zhang, Zishi School of Electronic and Information Engineering Beijing Jiaotong University Beijing China

ISBN: (纸本)9798331533694

With the advancement of Software-Defined Networking (SDN) technology, network programmability and flexibility have been significantly enhanced. However, effectively integrating traditional network systems with emerging programmable platforms remains a critical research challenge. this paper proposes a fusion architecture based on the P4Runtime protocol to achieve deep integration of SONiC white box switches and the P4 platform. By introducing SDN programmability, we design and implement a hybrid model that enables traditional network architectures to achieve advanced functionalities with the assistance of external SDN controllers. this paper provides a detailed discussion of the architecture design and implementation process, including P4 code development, compilation, target configuration file generation, and interaction mechanisms between the control plane and the data plane. Furthermore, we validate the applicability and performance of the architecture in various scenarios, offering robust support for future research and applications in programmable networks. © 2025 ieee.

关键词： Internet protocols

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A Frequency Calculation and Temperature Compensation System for Quartz Resonant Accelerometer Sensors 4

A Frequency Calculation and Temperature Compensation System ...

引用

4th international Computational Imaging conference, CITA 2024

作者： Zheng, De-Zhi Li, Zong-Lin Hu, Chun Wang, Yi-Lin Liu, Bei Advanced Research-Institute of Multidisciplinary Sciences Beijing Institute of Technology Beijing100081 China State Key Laboratory of CNS/ATM Beijing-Institute of Technology Beijing100081 China MllT Key Laboratory of Complex-field-Intelligent Exploration Beijing Institute of Technology Beijing100081 China Beijing Research Institute of Telemetry China

ISBN: (纸本)9781510688834

Acceleration sensors determine the accuracy and reliability of the inertial measurement system. In quartz acceleration sensors, the frequency calculation method directly affects their performance. the current research focuses on improving the signal processing algorithm, optimizing the sensor hardware design and its frequency calculation method as well as temperature compensation. However, there are still some limitations in stability and accuracy. To address these challenges, this paper introduces an optimized frequency calculation module based on a field-programmable Gate Array (FPGA). the resonant acceleration sensor calculates the acceleration by measuring the resonant frequency difference between the upper and lower beams. the optimization module utilizes the equal precision sampling technology to effectively reduce the ±1 error of the frequency measurement signal, and by optimizing the gating time, improve the speed and accuracy of frequency measurement. the system clock subdivision techniques are employed to reduce system errors further. the frequency characteristics of quartz resonators are investigated in this paper. the optimal polynomial order for compensation is determined by polynomial fitting using the least square method. Based on the above, this paper builds a complete hardware-software system. the system uses FPGA to construct a programmable Chip (SOPC) and its duties involve frequency monitoring, data interaction, frequency calculation, and temperature compensation. System measurement results showed an accuracy of 46.98 mHz at 400 Hz and 2.96 mHz at 1 Hz. the frequency temperature adjustment method decreased the maximum offset of zero deviation dynamic frequency from 26.0192Hz to 0.3836Hz over the entire temperature range (- 40 to 80°C). © 2025 SPIE.

关键词： Accelerometers

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Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping 38

Enhancing Reliability and Energy Efficiency in Network-on-Ch...

引用

38th international conference on VLSI Design, VLSID 2025

作者： Reddy, B. Naresh Kumar Jogi, Srinivasulu Krishna, Y. Charan NIT Tiruchirappalli Department of ECE Tiruchirappalli India

ISBN: (纸本)9798331522445

Reliability and energy efficiency are critical challenges in the design of modern Network-on-Chip (NoC) architectures, where the efficient mapping of computational tasks to processing cores plays a pivotal role in overall system performance. To address these challenges, A hybrid sorting algorithm-based core mapping strategy that combines Bitonic and Selection sorters has been proposed. the Bitonic sorter is employed for high-throughput, parallel sorting of task sequences, ensuring an efficient initial task placement. Subsequently, the Selection sorter refines the mapping by focusing on core reliability and energy efficiency, operating in a dual-mode that adapts to varying workload demands. this hybrid approach significantly reduces communication overhead, minimizes energy consumption, and enhances the overall reliability of NoC systems. A field programmable Gate Array (FPGA) was used to measure performance metrics such as application runtime, area, and onchip power consumption. Experimental results using synthetic and real-world benchmarks demonstrate the effectiveness of the proposed algorithm, showcasing its potential to optimize task-to-core mappings for next-generation NoC designs, © 2025 ieee.

关键词： field programmable gate arrays (FPGA)

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Next-Generation Smart Greenhouse: Integrating Universal Interaction Technologies 4

Next-Generation Smart Greenhouse: Integrating Universal Inte...

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4th international conference on Robotics, Electrical and Signal Processing Techniques, ICREST 2025

作者： Hassan, Tonmoy Das, Debraj Ahmad, Shameem Murad, Sayed Hasan Hazari, Md. Rifat Rahman Zishan, Md. Saniat Hossain, Tamim American International University-Bangladesh Faculty of Engineering Department of Electrical and Electronic Engineering Dhaka1229 Bangladesh American International University-Bangladesh Dhaka1229 Bangladesh

ISBN: (纸本)9798331530938

Agriculture is the largest employment sector in Bangladesh, making up 14.2% of GDP in 2017 and employing about 42.7% of the workforce. To support the GDP and grater employment, uses of the latest technology in agricultural areas are much more needed. Farmers still using the convention way to grow crops, which leads to less production, high labor cost, more manpower needed to monitor and maintenance the yield system. this study focuses on IoT-based smart greenhouse agricultural monitoring and automation, which provides farmers with real-time data and insights into a variety of topics such as data monitoring, controlling, automation crop yield, and cost effectiveness. An ESPS266-based hardware and Adafruit platform have been designed to monitor extracted data such as soil moisture, temperature, humidity, automatic water irrigation and automatic hot air exhaust systems. the system's benefit is proved in a comprehensive manner through defined programming, hardware results, and data analysis, reducing the need for human monitoring and watering of the system, hot air will be expelled from the field, resulting in greater crop development up to 15-50% higher crop yield on the same field. © 2025 ieee.

关键词： Soil moisture

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Multimodal MEMS Microwrinkle Electronics for Cardiac Pulsed field Ablation and Sensing 38

Multimodal MEMS Microwrinkle Electronics for Cardiac Pulsed ...

引用

38th ieee international conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Xu, Mengfei Peng, Quan Song, Ziliang Qin, Mu Sun, Yimeng Du, Zhiyuan Zheng, Kunyu Wang, Xiaolin Yang, Bin Liu, Jingquan Shanghai Jiao Tong University National Key Laboratory of Advanced Micro and Nano Manufacture Technology Shanghai China Shanghai Jiao Tong University Dci Joint Team Collaborative Innovation Center of Ifsa Department of Micro/Nano Electronics Shanghai China Shanghai Jiao Tong University Shanghai Chest Hospital School of Medicine Department of Cardiology Shanghai China Shanghai University of Electric Power Shanghai China

ISBN: (纸本)9798331508890

this paper reports a multimodal MEMS electronic device (MMED) with microwrinkle structures for pulsed field ablation (PFA), pH sensing, ECG recording and electrical pacing in cardiac surgery. Taking advantage of stress unconcentration during the curing of PDMS, microwrinkles with a characteristic size of 10 μm on electrodes are obtained, which facilitates improved electrical stimulation and recording capabilities. Further, IrOx coating on microwrinkle electrodes by lift-off process improves the electrochemical performance. the pH sensitivity of IrOx electrodes is up to 51.03 mV/pH. By using living rats, we show that the device with stretchable designs can establish conformal contact with curved heart surfaces, support high-quantity ECG recording and programmable electrical pacing. Meanwhile, the effectiveness of PFA is successfully performed on living swine hearts by thoracotomy. Integrating MEMS multimodal technologies into medical instruments may improve surgical performance and patient well-being. © 2025 ieee.

关键词： Ablation

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Low Area Design and Implementation of Lightweight Encryption Algorithm on FPGA for IoT Devices

Low Area Design and Implementation of Lightweight Encryption...

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AI in Cybersecurity (ICAIC), international conference on

作者： Keshav Kumar Dr Chinnaiyan Ramasubramanian Bishwajeet Pandey Department of E.C.E Lingaya’s Vidyapeeth (Deemed-to-be University) Faridabad Haryana India Department of MCA GL Bajaj College of Technology and Management Greater Noida India

ISBN: (数字)9798331518882

ISBN: (纸本)9798331518899

the increasing necessity for secure communication in resource-constrained platforms those found in the Internet of things (IoT), has drawn to a key spike in demand for lightweight symmetric cyphers. However, a number of numerous algorithms and implementation are available and, selecting the best security solution for a given application is still difficult. the implementation of Lightweight Advanced Encryption Standard (LAES) algorithms on hardware is the main concern of this work which will be suited for the IoT devices. In this work LAES is implemented to satisfy the security requirements for the IoT devices. Kintex 7 FPGA (field programmable Gate Array) is used for the implementation, and key performance metrices including hardware area utilization are used to assess the performance. the results determine prominent improvements in accomplishing compact, area-efficient designs. there is a decrement of $\mathbf{7 3. 1 0 \%}$ in LUT consumption as compared with exiting approaches.

关键词： Performance evaluation Logic gates Hardware Table lookup Encryption Internet of things Hardware design languages field programmable gate arrays Optimization Standards

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Hardware-Efficient Polar Decoder for 5G Internet of things Communication 9th

Hardware-Efficient Polar Decoder for 5G Internet of Things C...

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9th international conference on Intelligent IoT as a Service

作者： Guo, Jing Li, Congduan Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen Peoples R China

ISBN: (纸本)9783031705069;9783031705076

Polar codes have aroused extensive attention due to their capacity-achieving property and low encoding and decoding complexity. With the increasing demand for real-time and high-quality applications, achieving low-latency communication in resource-constrained scenarios such as on Internet of things (IoT) devices has become essential. this paper proposes a modified semi-parallel decoder for 5G IoT communication, with low decoding latency and high efficiency of hardware resources. 4-bit decoding algorithm and look-ahead approach are used in this work to reduce latency caused by conventional semi-parallel architecture. For a code length of N = 2(10), the proposed decoder improves latency by 48.64% and 75.19% than the conventional semi-parallel decoder and 2-bit decoder, separately. the significant improvement in hardware utilization rate of processing elements by 68.42% and 119.35% leads to high efficiency of hardware resources.

关键词： Internet of things Polar codes Wireless communication Hardware architecture field programmable gate array

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