thE Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and imageprocessing. the system can achieve 20 Giga-flops ...
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A non-linear projection method is presented to visualize high-dimensional data as a two-dimensional image. the proposed method is based on the topology preserving mapping algorithm of Kohonen [1-3]. this algorithm is ...
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Describes the design and implementation of a two-dimensional systolic array processor for applications in imageprocessing and computervision. the processor architecture is based on a SIMD array of 4-bit processing e...
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Describes the design and implementation of a two-dimensional systolic array processor for applications in imageprocessing and computervision. the processor architecture is based on a SIMD array of 4-bit processing elements, interconnected by a mesh network with four nearest neighbors. the PE array is programmable allowing the user to develop application-specific algorithms for performing analysis on image data. A prototype VLSI chip has been designed implementing a single PE and has been submitted for fabrication. the chip is expected to operate at 25 MHz.< >
To overcome the main drawbacks of parallel SIMD imageprocessing architectures, a new computer, called SYMPATIX, is proposed. the authors' goal is to implement low and intermediate levels of imageprocessing on a ...
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To overcome the main drawbacks of parallel SIMD imageprocessing architectures, a new computer, called SYMPATIX, is proposed. the authors' goal is to implement low and intermediate levels of imageprocessing on a SIMD computer. A study leads us to propose a network establishing asynchronous communications in a synchronous parallel structure. the performances of SYMPATIX have been evaluated on a VHDL model of the new computer. the machine supports imageprocessing operations and image transforms. the design of the circuits is under progress using electronic synthesis tools.< >
Describes an implementation of a processor node on a Texas Instruments EVM16 microprogrammable machine. In addition, the authors give an algorithm for performing morphological imageprocessing-a commonly used image pr...
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Describes an implementation of a processor node on a Texas Instruments EVM16 microprogrammable machine. In addition, the authors give an algorithm for performing morphological imageprocessing-a commonly used imageprocessing tool today-on such a distributed control architecture. Finally, they give an overview of a software simulator being implemented for simulating the whole pyramid machine. A simulator is essential for testing the working of the architecture and the algorithms before building the hardware.< >
Deals withthe hardware implementation of a low-level imageprocessing unit for mobile autonomous systems. High processing performance and a small physical size of the sensor and processing unit are two important fact...
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Deals withthe hardware implementation of a low-level imageprocessing unit for mobile autonomous systems. High processing performance and a small physical size of the sensor and processing unit are two important factors. the imageprocessing unit described here combines between high system performance and flexibility. the emphasis for this design lies on two aspects, i.e. adapted processors, in this case SIMD processor-arrays, and guided data reduction by means of finding partial images.< >
Production system programs are being routinely used in diverse tasks. Withthe increasing acceptance, demands on production system implementations is growing. Currently several research efforts are trying to use produ...
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the performance of the ASP computer on vision tasks has been evaluated by applying the Abingdon Cross benchmark using a number of different algorithms. In this paper, these algorithms are compared and contrasted on th...
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the performance of the ASP computer on vision tasks has been evaluated by applying the Abingdon Cross benchmark using a number of different algorithms. In this paper, these algorithms are compared and contrasted on the basis of their performance.< >
An architecture is presented for low-cost and flexible realisation of imageprocessing and analysis algorithms of binary images. the flexibility of the architecture is due to reconfigurable network of simple boolean f...
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An architecture is presented for low-cost and flexible realisation of imageprocessing and analysis algorithms of binary images. the flexibility of the architecture is due to reconfigurable network of simple boolean functions. It is shown that this architecture can readily be implemented by low-cost off-the-shelf components. this is illustrated by some simulations of a hypothetical realisation.< >
Window-based parallel architectures are considered as target structures for the computation of low and medium level imageprocessing algorithms. their definition stems from a general reformulation of algorithms, based...
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Window-based parallel architectures are considered as target structures for the computation of low and medium level imageprocessing algorithms. their definition stems from a general reformulation of algorithms, based on local data processing. A methodology for high level global evaluation of such architectures is presented, considering the reachable performances of the structures as main significant parameters.< >
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