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4th international symposium on code generation and optimization

作者： Das, Abhinav Lu, Jiwei Hsu, Wei-Chung Univ Minnesota Minneapolis MN 55455 USA

ISBN: (纸本)0769524990

Dynamic optimization relies on phase detection for two important functions (1) To detect change in code working set and (2) To detect change in performance characteristics that can affect optimization strategy. Current prototype runtime optimization systems [12][13] compare aggregate metrics like CPI over fixed time intervals to detect a change in working set and a change in performance. While simple and cost-effective, these metrics are sensitive to sampling rate and interval size. A phase detection scheme that computes performance metrics by aggregating the performance of individually optimized regions can be misled by some regions impacting aggregate metrics adversely. In this paper we investigate the benefits and limitations of using aggregate metrics for phase detection, which we call Global Phase Detection (GPD). We present a new model to detect change in working set and propose that the scope of phase detection be limited to within the candidate regions for optimization. By associating phase detection to individual regions we can isolate the effects of regions that are inherently unstable. this approach, which we call Local Phase Detection (LPD), shows improved performance on several benchmarks even when global phase detection is not able to detect stable phases.

关键词： Monitoring Phase detection Aggregates Runtime Prototypes Hardware Counting circuits Sampling methods Measurement Sun

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A self-repairing prefetcher in an event-driven dynamic optimization framework 06

A self-repairing prefetcher in an event-driven dynamic optim...

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4th international symposium on code generation and optimization

作者： Zhang, Weifeng Calder, Brad Tullsen, Dean M. Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA

ISBN: (纸本)0769524990

Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However to be effective, prefetching must target the most critical (frequently missing) loads, and prefetch them sufficiently far in advance. this is difficult to do correctly with a static optimizer because locality characteristics and cache latencies vary across data inputs and across different machines. this paper presents a mechanism that dynamically inserts prefetch instructions into frequently executed hot traces. Hot traces are dynamically analyzed to identify delinquent loads and the appropriate prefetch distance for those loads. those prefetches are then inserted into the hot trace. the low overhead of the event-driven dynamic optimization system allows the optimizer to continuously monitor the performance of the software prefetches. this is done to find an accurate and stable prefetch distance and to adapt to changes in program behavior using what we call Self-Repairing prefetching. Relative to the baseline hardware stride prefetching, we find a total 23% improvement when we use the self-repairing mechanism to adaptively discover the best prefetch distance for each load, which is 12% better performance than dynamic prefetching techniques without adaptive repairing.

关键词： Prefetching Delay Hardware Yarn Monitoring Software performance Computer science Power engineering and energy Bridges Computer architecture

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Using machine learning to focus iterative optimization 06

Using machine learning to focus iterative optimization

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4th international symposium on code generation and optimization

作者： Agakov, F. Bonilla, E. Cavazos, J. Franke, B. Fursin, G. O'Boyle, M. F. P. thomson, J. Toussaint, M. Williams, C. K. I. Univ Edinburgh Sch Informat Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)0769524990

Iterative compiler optimization has been shown to outperform static approaches. this, however is at the cost of large numbers of evaluations of the program. this paper develops a new methodology to reduce this number and hence speed up iterative optimization. It uses predictive modelling from the domain of machine learning to automatically focus search on those areas likely to give greatest performance. this approach is independent of search algorithm, search space or compiler infrastructure and scales gracefully with the compiler optimization space size. Off-line, a training set of programs is iteratively evaluated and the shape of the spaces and program features are modelled these models are learnt and used to focus the iterative optimization of a new program. We evaluate two learnt models, an independent and Markov model, and evaluate their worth on two embedded platforms, the Texas Instrument C6713 and the AMD Au1500. We show that such learnt models can speed up iterative search on large spaces by an order of magnitude. this translates into an average speedup of 1.22 on the TI C6713 and 1.27 on the AMD Au1500 in just 2 evaluations.

关键词： Machine learning Iterative methods Optimizing compilers Costs optimization methods Predictive models Machine learning algorithms Iterative algorithms Shape Instruments

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A cross-architectural interface for code cache manipulation 06

A cross-architectural interface for code cache manipulation

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4th international symposium on code generation and optimization

作者： Hazelwood, Kim Cohn, Robert Univ Virginia Charlottesville VA 22903 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)0769524990

Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentially-altered copy of every instruction that executes, run-time access to a code cache can be a very powerful opportunity Unfortunately, current research infrastructures lack the ability to model and direct code caching, and as a result, past code cache investigations have required access to the source code of the binary transformation system. this paper presents a code cache-aware interface to the Pin dynamic instrumentation system. While a program executes, our interface allows a user to inspect the code cache, receive callbacks when key events occur and manipulate the code cache contents at will. We demonstrate the utility of this interface on four architectures (IA32, EM64T IPF, XScale) and present several tools written using our AP1. these tools include a self-modifying code handler a two-phase instrumentation analyzer a code cache visualizer and custom code cache replacement policies. We also show that tools written using our interface have comparable performance to direct, source-level implementations. Both our interface and sample open-source tools that utilize the interface have been incorporated into the standard distribution of the Pin dynamic instrumentation engine, which has been downloaded over 5, 000 times in 18 months.

关键词： Instruments Runtime Robustness Application software Costs Power system modeling Visualization Open source software Engines Security

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thread-shared software code caches 06

Thread-shared software code caches

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4th international symposium on code generation and optimization

作者： Bruening, Derek Kiriansky, Vladimir Garnett, Timothy Banerji, Sanjeev Determina Inc.

ISBN: (纸本)0769524990

Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other tools. Despite the now-widespread use of code caches, techniques for efficiently sharing them across multiple threads have not been fully explored. Some systems simply do not support threads, while others resort to thread-private code caches. Although thread-private caches are much simpler to manage, synchronize, and provide scratch space for they simply do not scale when applied to many-threaded programs. thread-shared code caches are needed to target server applications, which employ hundreds of worker threads all performing similar tasks. Yet, those systems that do share their code caches often have brute-force, inefficient solutions to the challenges of concurrent code cache access: a single global lock on runtime system code and suspension of all threads for any cache management action. this limits the possibilities for cache design and has performance problems with applications that require frequent cache invalidations to maintain cache consistency. In this paper we discuss the design choices when building thread-shared code caches and enumerate the difficulties of thread-local storage, synchronization, trace building, in-cache lookup tables, and cache eviction. We present efficient solutions to these problems that both scale well and do not require thread suspension. We evaluate our results in DynamoRIO, an industrial-strength dynamic binary translation system, on real-world server applications. On these applications our thread-shared caches use an order of magnitude less memory and improve throughput by up to four times compared to thread private caches.

关键词： Yarn Dynamic compiler Buildings Software tools Runtime Optimizing compilers File servers Cache storage Table lookup throughput

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Exhaustive optimization phase order space exploration 06

Exhaustive optimization phase order space exploration

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4th international symposium on code generation and optimization

作者： Kulkarni, Prasad A. Whalley, David B. Tyson, Gary S. Davidson, Jack W. Florida State Univ Dept Comp Sci Tallahassee FL 32306 USA Univ Virginia Dept Comp Sci Charlottesville VA 22904 USA

ISBN: (纸本)0769524990

the phase-ordering problem is a long standing issue for compiler writers. Most optimizing compilers typically have numerous different code-improving phases, many of which can be applied in any order these phases interact by enabling or disabling opportunities for other optimization phases to be applied. As a result, varying the order of applying optimization phases to a program can produce different code, with potentially significant performance variation amongst them. Complicating this problem further is the fact that there is no universal optimization phase order that will produce the best code, since the best phase order depends on the function being compiled, the compiler, and the target architecture characteristics. Moreover, finding the optimal optimization sequence for even a single function is hard as the space of attempted optimization phase sequences is huge and the interactions between different optimizations are poorly understood. Most previous studies performed to search for the most effective optimization phase sequence assume the optimization phase order search space to be extremely large, and hence consider exhaustive exploration of this space infeasible. In this paper we show that even though the attempted search space is extremely large, with careful and aggressive pruning it is possible to limit the actual search space with no loss of information so that it can be completely evaluated in a matter of minutes or a few hours for most functions. We were able to exhaustively enumerate all the possible function instances that can be produced by different phase orderings performed by our compiler for more than 98% of the functions in our benchmark suite. In this paper we describe the algorithm we used to make exhaustive search of the optimization phase order space possible. We then analyze this space to automatically calculate relationships between different phases. Finally, we show that the results of this analysis can be used to reduce the compilation

关键词： Space exploration Optimizing compilers Computer science Program processors Lifting equipment Performance analysis Energy consumption

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Selecting software phase markers with code structure analysis 06

Selecting software phase markers with code structure analysi...

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4th international symposium on code generation and optimization

作者： Lau, Jeremy Perelman, Erez Calder, Brad Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA

ISBN: (纸本)0769524990

Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program's execution into phases, where samples of execution in the same phase have homogeneous behavior and similar resource requirements. In this paper we present an automated profiling approach to identify code locations whose executions correlate with phase changes. these "sofiware phase markers" can be used to easily detect phase changes across different inputs to a program without hardware support. Our approach builds a combined hierarchical procedure call and loop graph to represent a program's execution, where each edge also tracks the max, average, and standard deviation in hierarchical execution variability on paths from that edge. We search this annotated call-loop graph for instructions in the binary that accurately identify the start of unique stable behaviors across different inputs. We show that our phase markers can be used to accurately partition execution into units of repeating homogeneous behavior by counting execution cycles and data cache hits. We also compare the use of our software markers to prior work on guiding data cache reconfiguration using data-reuse markers. Finally, we show that the phase markers can be used to partition the program's execution at code transitions to pick accurately simulation points for SimPoint. When simulation points are defined in terms of phase markers, they can potentially be re-used across inputs, compiler optimizations, and different instruction set architectures for the same source code.

关键词： Hardware Optimizing compilers Clustering algorithms Computer science Phase detection Tracking loops Program processors Acceleration Heuristic algorithms Pattern analysis

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Profiling over adaptive ranges 06

Profiling over adaptive ranges

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4th international symposium on code generation and optimization

作者： Mysore, Shashidhar Agrawal, Banit Sherwood, Timothy Shrivastava, Nisheeth Suri, Subhash Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

ISBN: (纸本)0769524990

Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. this presents a serious challenge to those who seek to quantify, analyze, or optimize such systems, because important trends and behaviors may easily be lost in a sea of data. We present Range Adaptive Profiling (RAP) as a new and general purpose profiling method capable of hierarchically classifying streams of data efficiently in hardware. through the use of RAP, events in an input stream are dynamically classified into increasingly precise categories based on the frequency with which they occur the more important a class, or range of events, the more precisely it is quantified. Despite the dynamic nature of our technique, we build upon tight theoretic bounds covering both worst-case error as well as the required memory. In the limit, it is known that error and the memory bounds can be independent of the stream size, and grow only linearly with the level of precision desired. Significantly, we expose the critical constants in these algorithms and through careful engineering, algorithm re-design, and use of heuristics, we show how a high performance profile system can be implemented for Range Adaptive Profiling. RAP can be used on various profiles such as PCs, load values, and memory addresses, and has a broad range of uses, from hot-region profiling to quantifying cache miss value locality. We propose two methods of implementation, one in software and the other with specialized hardware, and we show that with just 8k bytes of memory range profiles can be gathered with an average accuracy of 98%.

关键词： Hardware Computer science Computer aided instruction Frequency Personal communication networks Design optimization Dynamic scheduling Load management Dynamic compiler Energy management

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Check-irregular LDPC codes for unequal error protection under iterative decoding 4

Check-irregular LDPC codes for unequal error protection unde...

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4th international symposium on Turbo codes and Related Topics and 6th international ITG-Conference on Source and Channel Coding, TURBOCODING 2006

作者： Sassatelli, Lucile Henkel, Werner Declercq, David International University Bremen Campus Ring 1 Bremen28759 Germany ETIS ENSEA UCP CNRS UMR-8051 6 avenue du Ponceau Cergy95014 France

ISBN: (纸本)3800729474

In many optimization techniques of LDPC codes, the check node irregularity is usually considered as being fixed because the profile must contain only two consecutive degrees in order to maximize the overall convergence speed of the code. We show in this paper that it is possible to construct bit-regular codes with more than two different degrees at check nodes side to speed up the convergence of some parts of the codeword, even if we may decrease a little the global convergence. then, we take advantage of the check irregularity to create unequal error protection (UEP) codes, and present a very flexible method to achieve it. this method is based on pruning a mother code, thereby creating different subcodes with different UEP properties, but decoded with the same decoder. © 2020 TURBO - CODING 2006 - 4th international symposium on Turbo codes and Related Topics and 6th international ITG-Conference on Source and Channel Coding. All rights reserved.

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generation of turbulent inflow conditions for large eddy simulation from stereoscopic PIV measurements

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international JOURNAL OF HEAT AND FLUID FLOW 2006年第4期27卷 576-584页

作者： Perret, Laurent Delville, Joel Manceau, Remi Bonnet, Jean-Paul Univ Poitiers CEAT ENSMA Lab Etud AerodynamCNRSUMR 6609 F-86036 Poitiers France

A novel method to generate inflow data for unsteady numerical simulations is proposed. this method consists in coupling an experimental database obtained by stereoscopic PIV measurements which are under-resolved in time to a numerical code. Based on the proper orthogonal decomposition of this database, the proposed approach enables the adaptation of the experimental mesh to the grid of the simulation and the modelling of the temporal dynamics of the flow field in the inlet section by Gaussian random time series that present the correct one- and two-point statistics. To test this method, a LES of a turbulent plane mixing layer configuration is performed. (C) 2006 Elsevier Inc. All rights reserved.

关键词： inflow conditions large eddy simulation particle image velocimetry mixing layer

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