检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,672 篇 会议
122 篇 期刊文献
22 册 图书

馆藏范围

3,816 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2,671 篇 工学
- 2,547 篇 计算机科学与技术...
- 1,152 篇 软件工程
- 412 篇 信息与通信工程
- 411 篇 电气工程
- 207 篇 电子科学与技术（可...
- 136 篇 控制科学与工程
- 78 篇 网络空间安全
- 40 篇 动力工程及工程热...
- 37 篇 机械工程
- 37 篇 建筑学
- 33 篇 生物医学工程（可授...
- 29 篇 光学工程
- 29 篇 生物工程
- 28 篇 土木工程
- 22 篇 仪器科学与技术
- 20 篇 化学工程与技术
- 20 篇 安全科学与工程
- 18 篇 力学（可授工学、理...
634 篇 理学
- 493 篇 数学
- 88 篇 物理学
- 67 篇 统计学（可授理学、...
- 56 篇 系统科学
- 35 篇 生物学
- 31 篇 化学
402 篇 管理学
- 339 篇 管理科学与工程(可...
- 157 篇 工商管理
- 84 篇 图书情报与档案管...
28 篇 医学
- 25 篇 临床医学
26 篇 经济学
- 25 篇 应用经济学
18 篇 法学
- 18 篇 社会学
12 篇 农学
6 篇 教育学
3 篇 文学
1 篇 军事学
1 篇 艺术学

主题

348 篇 parallel process...
302 篇 application soft...
238 篇 distributed comp...
208 篇 computer archite...
204 篇 concurrent compu...
197 篇 hardware
181 篇 computational mo...
177 篇 parallel process...
172 篇 graphics process...
171 篇 computer science
129 篇 runtime
120 篇 parallel program...
104 篇 processor schedu...
103 篇 distributed comp...
101 篇 distributed proc...
100 篇 grid computing
97 篇 scalability
96 篇 high performance...
96 篇 delay
94 篇 libraries

机构

12 篇 school of comput...
12 篇 ohio state univ ...
10 篇 argonne natl lab...
9 篇 univ chinese aca...
9 篇 hiroshima univ d...
9 篇 oak ridge natl l...
7 篇 ibm thomas j. wa...
7 篇 oak ridge nation...
7 篇 univ warwick dep...
7 篇 carnegie mellon ...
7 篇 department of co...
7 篇 ibm corp thomas ...
6 篇 oak ridge natl l...
6 篇 iit dept comp sc...
6 篇 lawrence berkele...
6 篇 georgia inst tec...
6 篇 department of co...
6 篇 univ coll dublin...
6 篇 department of co...
6 篇 department of co...

作者

20 篇 nakano koji
17 篇 lastovetsky alex...
16 篇 ito yasuaki
11 篇 dongarra jack
11 篇 jarvis stephen a...
11 篇 sun xian-he
11 篇 agrawal gagan
10 篇 wolf felix
9 篇 schulz martin
9 篇 guo minyi
9 篇 robert yves
8 篇 hoefler torsten
8 篇 h. casanova
8 篇 jack dongarra
8 篇 prasad sushil k.
8 篇 casanova henri
8 篇 magoules frederi...
8 篇 kale laxmikant v...
8 篇 labarta jesus
7 篇 bader david a.

语言

3,808 篇 英文
6 篇 其他
1 篇 土耳其文
1 篇 中文

检索条件"任意字段=4th International Symposium on Parallel and Distributed Processing and Applications"

共 3816 条记录，以下是111-120 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

REGAL : Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM 56

REGAL : Reprogrammable Engines for Genome Analysis on LPDDR4...

引用

56th IEEE international symposium on Circuits and Systems (ISCAS)

作者： Sinha, Aman Fang, Yuhao Lai, Bo-Cheng Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu Taiwan

ISBN: (纸本)9781665451093

Genomic big data analysis pipelines are bottlenecked with massive data movement between CPU and memory hierarchy. Recently developed Stacked Embedded DRAM (SEDRAM) with high density hybrid bonding offers not only high bandwidth concurrent data accesses, but also highly parallel distributed data processing on the logic layer. However, the complex logical flow and data dependencies pose challenges to existing Near-DRAM processing (NDP) solutions for analysis such as string pattern matching using FM-Index. In this work, we propose REGAL, a highly scalable and re-programmable solution on SEDRAM memory system. REGAL architecture maximizes intra-query parallelism and enhances occupancy of all components. the efficient data layout and mapping minimizes round-trip communications between processing engines. the programmability of REGAL further enables effective prefetching to support variations in data characteristics and involved algorithms. REGAL demonstrates up-to 17.3x and 70.6x speedup and energy reductions compared to multithreaded CPU implementation for FM-Index queries, while achieving performance comparable to state-of-the-art fixed-function NDP implementation.

关键词： FM-Index Near-DRAM processing SEDRAM RISC-V NoC processing-In-Memory Genome analysis

来源：评论

学校读者我要写书评

暂无评论

Efficient VLSI Architectures of Multimode 2D FIR Filter Bank using distributed Arithmetic Methodology 6th

Efficient VLSI Architectures of Multimode 2D FIR Filter Bank...

引用

6th international Conference on Soft Computing and Signal processing, ICSCSP 2023

作者： Odugu, Venkata Krishna Satish, B. Janardhana Rao, B. Gade, Harish Babu Department of ECE CVR College of Engineering Hyderabad India

ISBN: (纸本)9789819984503

For the implementation of the hardware structure of filter architecture, the area, power, and delay efficiency are needed. Memory complexity is also important in the 2D FIR filter architecture, while used for image processing applications. In this work, a memory-efficient 2D FIR filter bank architecture is designed using parallel processing, symmetry, and distributed arithmetic methodology. the symmetry concept decreases the quantity of the multipliers of the filter architecture. parallel processing and multimode filter bank approaches will improve memory efficiency through memory reuse and memory sharing, respectively. the distributed arithmetic (DA)-based filter architectures reduce the multiplier complexity in terms of power and area. Four types of symmetry filter architectures along with one normal filter (without symmetry) are integrated as a multimode filter bank. the required filter can be selected by the control logic. In this filter bank, the memory module is shared by all the sub-filter, which is called memory sharing. the LUT-based DA methodology is used to implement the multipliers of each sub-filter arithmetic module. the proposed multimode filter bank architecture is implemented for the filter length N = 4 with two-level parallel processing using Xilinx Vivado tools. the utilization of resources is correlated with works mentioned in the literature. the area, timing delay and power consumption reports are generated using Genus synthesis tools in 45 nm CMOS technology from the Cadence vendor. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Filter banks

来源：评论

学校读者我要写书评

暂无评论

the MIT Supercloud Workload Classification Challenge 36

The MIT Supercloud Workload Classification Challenge

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Tang, Benny J. Chen, Qiqi Weiss, Matthew L. Frey, Nathan C. McDonald, Joseph Bestor, David Yee, Charles Arcand, William Bergeron, William Byun, Chansup Edelman, Daniel Houle, Michael Hubbell, Matthew Jones, Michael Kepner, Jeremy Klein, Anna Michaleas, Adam Michaleas, Peter Milechin, Lauren Mullen, Julia Prout, Andrew Reuther, Albert Rosa, Antonio Bowne, Andrew McEvoy, Lindsey Li, Baolin Tiwari, Devesh Gadepally, Jiay Samsi, Siddharth MIT 77 Massachusetts Ave Cambridge MA 02139 USA MIT Lincoln Lab 244 Wood St Lexington MA 02173 USA Northeastern Univ Boston MA 02115 USA US Air Force Cambridge MA USA

ISBN: (纸本)9781665497473

High-Performance Computing (HPC) centers and cloud providers support an increasingly diverse set of applications on heterogenous hardware. As Artificial Intelligence (AI) and Machine Learning (ML) workloads have become an increasingly larger share of the compute workloads, new approaches to optimized resource usage, allocation, and deployment of new AI frameworks are needed. By identifying compute workloads and their utilization characteristics, HPC systems may be able to better match available resources with the application demand. By leveraging datacenter instrumentation, it may be possible to develop AI-based approaches that can identify workloads and provide feedback to researchers and datacenter operators for improving operational efficiency. To enable this research, we released the MIT Supercloud Dataset, which provides detailed monitoring logs from the MIT Supercloud cluster. this dataset includes CPU and GPU usage by jobs, memory usage, and file system logs. In this paper, we present a workload classification challenge based on this dataset. We introduce a labelled dataset that can be used to develop new approaches to workload classification and present initial results based on existing approaches. the goal of this challenge is to foster algorithmic innovations in the analysis of compute workloads that can achieve higher accuracy than existing methods. Data and code will be made publicly available via the Datacenter Challenge website : https://***.

关键词： Technological innovation distributed processing File systems Instruments High performance computing Graphics processing units Machine learning

来源：评论

学校读者我要写书评

暂无评论

parallel Approximations of the Tukey g-and-h Likelihoods and Predictions for Non-Gaussian Geostatistics 36

Parallel Approximations of the Tukey g-and-h Likelihoods and...

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Mondal, Sagnik Abdulah, Sameh Ltaief, Hatem Sun, Ying Genton, Marc G. Keyes, David E. King Abdullah Univ Sci & Technol Comp Elect & Math Sci & Engn Div Thuwal 239556900 Saudi Arabia King Abdullah Univ Sci & Technol Stat Program Thuwal Saudi Arabia King Abdullah Univ Sci & Technol Extreme Comp Res Ctr Thuwal Saudi Arabia

ISBN: (纸本)9781665481069

Maximum likelihood estimation is an essential tool in the procedure to impute missing data in climate/weather applications. By defining a particular statistical model, the maximum likelihood estimation can be used to understand the underlying structure of given geospatial data. the Gaussian random field has been widely used to describe geospatial data, as one of the most popular models under the hood of maximum likelihood estimation. Computation of Gaussian log-likelihood demands operations on a dense symmetric positive definite matrix, often parameterized by the Mat ' ern correlation function. this computation of the log-likelihood requires O( n2) storage and O( n3) operations, which can be a huge task considering that the number of geographical locations, n, now commonly reaches into the millions. However, despite its appealing theoretical properties, the assumptions of Gaussianity may be unrealistic since real data often show signs of skewness or have some extreme values. Herein, we consider the Tukey g-and-h (TGH) random field as an example of a non-Gaussian random field that shows more robustness in modeling geospatial data by including two more parameters to incorporate skewness and heavy tail features in the model. this work provides the first HPC implementation of the TGH random field's inference on parallel hardware architectures. Using task-based programming models associated with dynamic runtime systems, our implementation leverages the high concurrency of current parallel systems. this permits to run the exact log-likelihood evaluation of the Tukey g-and-h (TGH) random fields for a decent number of geospatial locations. To tackle large-scale problems, we provide additionally an implementation of the given model using two different lowrank approximations. We compress the aforementioned positivedefinite symmetric matrix for computing the log-likelihood and rely on the Tile Low-Rank (TLR) and the Hierarchical OffDiagonal Low-Rank (HODLR) matrix approximatio

关键词： Maximum likelihood estimation Symmetric matrices Runtime Computational modeling Linear algebra Tail Predictive models

来源：评论

学校读者我要写书评

暂无评论

Efficient Large Scale Reverse-time Migration Imaging Computation based on distributed Spark Cluster with GPUs 21

Efficient Large Scale Reverse-time Migration Imaging Computa...

引用

21st IEEE international symposium on parallel and distributed processing with applications, 13th IEEE international Conference on Big Data and Cloud Computing, 16th IEEE international Conference on Social Computing and Networking and 13th international Conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Wangzhang, Suhui Yang, Ruizhang Gu, Rong Li, Bo Liu, Dingjin Wang, Zhaokang Nanjing University State Key Laboratory for Novel Software Technology China Sinopec Geophysical Research Institute China Nanjing University of Aeronautics and Astronautics College of Computer Science and Technology China

ISBN: (纸本)9798350329223

the reverse-time migration (RTM) imaging algorithm, which is used for complex underground structure analysis, is known as one of the current mainstream method of high-precision seismic imaging. Nowadays, as the fast development of seismic data acquisition technology, there exists large amount of seismic data. thus, the requirement for the efficient computation of the reverse-time migration (RTM) imaging algorithms over large-scale data have been increased greatly. To address this problem, in this paper, we propose a distributed reverse-time migration imaging algorithm based on the widely-used Spark platform first. Based on that, we design and implement a RTM computation solution based on Spark and GPU with several optimizations, including pre-shuffle&caching and load balancing. We also analyze the fault tolerance capability of the proposed distributed algorithm. We evaluate the proposed methods on the typical three-dimensional wavefild benchmark dataset. Experimental results show that the performance of the Spark based reverse-time migration imaging algorithm can scale up near linearly with computing nodes. In addition, the GPU+Spark based version has significant performance improvement on execution efficiency over the Spark-based algorithm. Moreover, the proposed optimization strategies also take effect. In addition, the method proposed in this paper has been applied in the real-world environment of one of the top oil exploration companies world wide, and has achieved significant improvement under the premise of the algorithm correctness guarantee. © 2023 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

MLCNN: Cross-Layer Cooperative Optimization and Accelerator Architecture for Speeding Up Deep Learning applications 36

MLCNN: Cross-Layer Cooperative Optimization and Accelerator ...

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Jiang, Beilei Cheng, Xianwei Tang, Sihai Ma, Xu Gu, Zhaochen Fu, Song Yang, Qing Liu, Mingxiong Univ North Texas Denton TX 76203 USA Los Alamos Natl Lab Los Alamos NM USA

ISBN: (纸本)9781665481069

the ever-increasing number of layers, millions of parameters, and large data volume make deep learning workloads resource-intensive and power-hungry. In this paper, we develop a convolutional neural network (CNN) acceleration framework, named MLCNN, which explores algorithm-hardware co-design to achieve cross-layer cooperative optimization and acceleration. MLCNN dramatically reduces computation and on-off chip communication, improving CNN's performance. To achieve this, MLCNN reorders the position of nonlinear activation layers and pooling layers, which we prove results in a negligible accuracy loss;then the convolutional layer and pooling layer are co-optimized by means of redundant multiplication elimination, local addition reuse, and global addition reuse. To the best of our knowledge, MLCNN is the first of its kind that incorporates cooperative optimization across convolutional, activation, and pooling layers. We further customize the MLCNN accelerator to take full advantage of cross-layer CNN optimization to reduce both computation and on-off chip communication. Our analysis shows that MLCNN can significantly reduce (up to 98%) multiplications and additions. We have implemented a prototype of MLCNN and evaluated its performance on several widely used CNN models using both an accelerator-level cycle and energy model and RTL implementation. Experimental results show that MLCNN achieves 3.2x speedup and 2.9x energy efficiency compared with dense CNNs. MLCNN's optimization methods are orthogonal to other CNN acceleration techniques, such as quantization and pruning. Combined with quantization, our quantized MLCNN gains a 12.8x speedup and 11.3x energy efficiency compared with DCNN.

关键词： Deep learning Cross-layer optimization Accelerators Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML 22

Automatic Implementation of Large-Scale CNNs on FPGA Cluster...

引用

22nd IEEE international symposium on parallel and distributed processing with applications, ISPA 2024

作者： Lu, Yihang Qi, Xingyun Li, Yuan Lai, Mingche Zhao, Yankang Li, Zhenqi Li, Hanyuan Wang, Qiang National University of Defense Technology School of Computer Science Changsha China

ISBN: (纸本)9798331509712

Convolutional Neural Networks (CNNs) have demonstrated remarkable performance across various computer vision tasks. Due to the computational and data-intensive nature of CNNs, Field-Programmable Gate Arrays (FPGAs) are exceptionally well-suited for accelerating the CNN computation process. However, large-scale CNNs such as ResNet-84 contain an enormous number of parameters that exceed the capacity of a single FPGA, rendering the deployment on a single device impractical. In this paper, we develop an automated end-to-end design flow for mapping large-scale CNNs across multiple FPGAs, on the basis of the HLS4ML dataflow architecture. We propose a graph optimization method to streamline the CNN structure and reduce resource consumption. We also summarize a resource allocation algorithm that automatically determines the specific hardware resources necessary for each CNN layer. Furthermore, we introduce a partitioning methodology capable of effectively segmenting CNNs into multiple FPGAs, and providing each subgraph with specific interfaces to support communication between different FPGAs. To validate the methodology, we construct a multi-FPGA platform interconnected via LVDS. We select two typical networks, ResNet-8 and ResNet-84, as the benchmarks for evaluation. the experimental results demonstrate that our approach significantly outperforms existing solutions. It attains an 18.6-fold increase in speed over Vitis AI, a 2.2-fold improvement over FINN, and a 3.4-fold enhancement over the original single-FPGA HLS4ML implementation for ResNet-8. For ResNet-84, our method achieves a remarkable 33.6-fold speedup over Vitis AI. Additionally, when compared to other non-automated multi-FPGA solutions, our methodology still exhibits significant performance improvements. © 2024 IEEE.

关键词： Convolutional neural networks

来源：评论

学校读者我要写书评

暂无评论

Energy Efficiency through In-Sensor Computing: ADC-less Real-Time Sensing for Image Edge Detection 24

Energy Efficiency Through In-Sensor Computing: ADC-less Real...

引用

29th ACM / IEEE international symposium on Low Power Electronics and Design (ISLPED)

作者： Modak, Nirmoy Roy, Kaushik Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9798400706882

In-sensor computing has revolutionized modern vision-based applications, particularly in scenarios like autonomous vehicles and robotics where real-time or near-real-time processing is crucial. By enabling data processing at the sensor level, in-sensor computing eliminates the need to transmit data to cloud servers, significantly reducing latency and enhancing decision-making speed. Central to the in-sensor computing paradigm, CMOS image sensors (CISs) with edge computing, play a pivotal role in machine vision applications. the need for high resolution, low power, and real-time operation aligns seamlessly with the demands of modern vision-based applications. In this paper, we propose a novel approach for real-time image edge detection with an in-sensor, ADC-less sensing solution that achieves high energy efficiency and speed. the design utilizes the column-parallel architecture of existing CIS and the row-wise pixel readout scheme. Column voltages of three consecutive rows with a delay arrangement extract 4-bit edge pixels without deriving the actual digital image pixels. A time-to-digital conversion (TDC) technique using a 4-bit counter eliminates the requirement of power-hungry ADC. A 256(H) x 256(V) 2D CMOS pixel array with 10.. m pixel pitch is simulated using Spectre in TSMC 65nm low-power technology. CMOS pixels with wide dynamic range (WDR) capture the light intensity variation up to 92dB [10]. Simulation results show energy consumption of 2pWper pixel per frame, operating at a frame rate of 3.9kfps, all well-contained within a modest 0.5 mW power budget. the resultant frame rate emerges as notably superior in terms of speed, accompanied by a more than tenfold reduction in power consumption per edge frame-pixel compared to the existing prior art.

关键词： CMOS image sensor (CIS) column-parallel (CP) imaging Wide Dynamic Range (WDR) Image Signal Processor (ISP) time-to-digital conversion (TDC) ADC-less CIS On-chip image edge detection

来源：评论

学校读者我要写书评

暂无评论

Cost-Effective Dynamic Alliance Pricing Mechanism Based on distributed Edge-Intelligence 21

Cost-Effective Dynamic Alliance Pricing Mechanism Based on D...

引用

作者： Cao, Zhihan Zheng, Xi Guo, Jianxiong Jia, Weijia Xu, Yang Wang, Tian Beijing Normal University Zhuhai China Fudan University Shanghai China Macquarie University Australia Hunan University Changsha China

ISBN: (纸本)9798350329223

In Internet of thing (ToT) system based on edge intelligence, pay-for-use demand has become a consensus, and the pricing of ToT services has attracted the attention of academia and industry. the pricing method based on non-cooperative game allows edge service providers to compete fairly, effectively preventing edge nodes from malicious bidding. However, in this scenario, a task can only be assigned to one edge vendor. Because only one winner can profit each time, it is easy to create a large number of edge service providers who cannot profit for a long time due to insufficient incentives. To this end, a dynamic alliance pricing mechanism based on distributed edge-intelligence is proposed. Edge service providers can freely choose to form an edge dynamic alliance, which not only retains the independence of edge nodes, but also makes full use of the advantages of mutual cooperation between nodes. Tn order to prevent abnormal behaviors of edge nodes, we set up necessary restrictive rules. At the same time, we designed a privacy-enhanced joint pricing prediction algorithm to screen the alliance's candidate solutions to improve pricing efficiency and edge benefit. the experimental results show that, compared with the traditional game method, the performance of the mechanism we proposed improves the utilization rate of edge resources by 32.76%-61.37%. Meanwhile, the prediction accuracy was improved by 16.47%38.86%, and the average prediction time was reduced by 42.81 %-65.57%. © 2023 IEEE.

关键词： Profitability

来源：评论

学校读者我要写书评

暂无评论

Asynchronous distributed-Memory Triangle Counting and LCC with RMA Caching 36

Asynchronous Distributed-Memory Triangle Counting and LCC wi...

引用

36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Strausz, Andras Vella, Flavio Di Girolamo, Salvatore Besta, Maciej Hoefler, Torsten Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland Univ Trento Dept Engn & Comp Sci Trento Italy

ISBN: (纸本)9781665481069

Triangle count and local clustering coefficient are two core metrics for graph analysis. they find broad application in analyses such as community detection and link recommendation. To cope with the computational and memory demands that stem from the size of today's graph datasets, distributed-memory algorithms have to be developed. Current state-of-the-art solutions suffer from synchronization overheads or expensive pre-computations needed to distribute the graph, achieving limited scaling capabilities. We propose a fully asynchronous implementation for triangle counting and local clustering coefficient based on 1D partitioning, using remote memory accesses for transferring data and avoid synchronization. Additionally, we show how these algorithms present data reuse on remote memory accesses and how the overall communication time can be improved by caching these accesses. Finally, we extend CLaMPI, a software-layer caching system for MPI RMA, to include application-specific scores for cached entries and influence the eviction procedure to improve caching efficiency. Our results show improvements on shared memory, and we achieve 14x speedup from 4 to 64 nodes for the LiveJournal1 graph on distributed memory. Moreover, we demonstrate how caching remote accesses reduces total running time by up to 73% with respect to a non-cached version. Finally, we compare our implementation to TriC, the 2020 graph champion paper, and achieve up to 100x faster results for scale-free graphs.

关键词： asynchronous computing caching distributed computing local clustering coefficient RDMA triangle counting

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共382页 << < 8 9 10 11 12 13 14 15 16 17 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：