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检索条件"任意字段=4th International Symposium on Parallel and Distributed Processing and Applications"

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Extend PBFT Protocol with L-DAG 19

Extend PBFT Protocol with L-DAG

引用

19th IEEE international symposium on parallel and distributed processing with applications (IEEE ISPA)

作者： Song, Anping Dai, Yi Ji, Ruyi Song, Ziheng Shanghai Univ Sch Comp Engn & Sci Shanghai Peoples R China Univ Illinois Coll Engn Champaign IL 61820 USA Univ Illinois Coll Engn Urbana IL 61820 USA

ISBN: (纸本)9781665435741

the linear structure of blockchain ensures data security and credibility. But at the same time, it has become the performance bottleneck of the entire system, limiting the growth of the transaction processing rate. the inherent concurrency of directed acyclic graph (DAG) technology solves these problems, but it also brings new problems: blocks total order and ledger consistency. In this paper, we propose a Layer-based DAG (L-DAG) blockchain, which avoids the complex total ordering algorithms by keeping blocks in order between and within layers during the generation process. And we introduce the proportional-integral-derivative (PID) controller to dynamically control the width of layers by using in-degree and out-degree of blocks to achieve the consistency of ledger. We extend Practical Byzantine Fault Tolerance (PBFT) protocol in parallel based on the L-DAG structure and successfully apply it to consortium blockchain scenarios. the L-DAG blockchain structure is implemented through Hyperledger Fabric. Experimental results show that as the number of consensus threads increases, the TPS of L-DAG-based PBFT can grow with near-linear efficiency.

关键词： L-DAG Width control In/Out-degree parallel consensus Proportional-integral-derivative controller

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Portable distributed implementation of the parallel multipole tree algorithm

Portable distributed implementation of the parallel multipol...

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Proceedings of the 4th IEEE international symposium on High Performance distributed Computing

作者： Rankin, William T. Board Jr., John A. Duke Univ Durham United States

Several variants of parallel multipole-based algorithms have been implemented to further research in fields such as computational chemistry and astrophysics. We present a distributed parallel implementation of a multipole-based algorithm that is portable to a wide variety of applications and parallel platforms. Performance data are presented for loosely coupled networks of workstations as well as for more tightly coupled distributed multiprocessors, demonstrating the portability and scalability of the application to large number of processors.

关键词： distributed computer systems

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Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA 34

Performance Evaluation of Pipelined Communication Combined w...

引用

34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Fujita, Norihisa Kobayashi, Ryohei Yamaguchi, Yoshiki Ueno, Tomohiro Sano, Kentaro Boku, Taisuke Univ Tsukuba Ctr Computat Sci Tsukuba Ibaraki Japan Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781728174457

In recent years, much High Performance Computing (HPC) researchers attract to utilize Field Programmable Gate Arrays (FPGAs) for HPC applications. We can use FPGAs for communication as well as computation thanks to FPGA's I/O capabilities. HPC scientists cannot utilize FPGAs for their applications because of the difficulty of the FPGA development, however High Level Synthesis (HLS) allows them to use with appropriate costs. In this study, we propose a Communication Integrated Reconfigurable CompUting System (CIRCUS) to enable us to utilize high-speed interconnection of FPGAS from OpenCL. CIRCUS makes a fused single pipeline combining the computation and the communication, which hides the communication latency by completely overlapping them. In this paper, we present the detail of the implementation and the evaluation result using two benchmarks: pingpong benchmark and allreduce benchmark.

关键词： FPGA OpenCL HLS parallel computing inter-connection

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A parallel Packet processing Runtime System On Multi-Core Network Processors

A Parallel Packet Processing Runtime System On Multi-Core Ne...

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11th international symposium on distributed Computing and applications to Business, Engineering and Science (DCABES)

作者： Li, Yunchun Shan, Lianqiang Qiao, Xinxin BeiHang Univ Beijing Beijing Key Lab Network Technol Dept Comp Sci Beijing Peoples R China

ISBN: (纸本)9780769548180

More and more network devices and chips commonly apply multi-core architectures to meet increasingly performance demands. But the lack of efficient program level parallelism and workload allocation in the packet processing system greatly limits the utilization of multi-core architectures. In this paper, we propose a parallel packet processing runtime system and explore an affinity-based packet scheduler with the goal of raising load balancing and decreasing cache miss. We can use the system that handles the allocation of processing tasks to simplify the implementation of new applications. the experiment results show task distributor and scheduler can achieve a better compromise between load balancing and cache affinity in the parallel packet processing system.

关键词： multi-core load banlance parallel packet process

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Multi-core Portability Abstraction

Multi-core Portability Abstraction

引用

26th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Forsell, Martti Hiivala, Mikko VTT Tech Res Ctr Finland Platform Architectures Team FI-90571 Oulu Finland

ISBN: (纸本)9780769546766

Application portability between different multicore architecture-parallel programming paradigm/tool pairs is a big problem nowadays leading often to a complete rewrite of an application when switching from an architecture-paradigm pair to another. this is caused by a wide variety of architectural properties requiring different optimization techniques for different architectures, typically hiding the essence of (parallel) computation defined by the application. In this paper, we introduce the Multi-Core Portability Abstraction (MCPA) simplifying portability and implementation of parallel applications making use of shared memory. It abstracts away typical architecture dependent effects caused by latency, synchronization, and partitioning and acts as an executable intermediate abstraction/reference implementation as well as a tool for analyzing the intrinsic parallelism of the application and relative goodness of architectures in executing it. We give a short application example with performance measurements.

关键词： parallel computing multicore architectures model of computation parallel programming application portability

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Modeling Memory Contention between Communications and Computations in distributed HPC Systems 36

Modeling Memory Contention between Communications and Comput...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Denis, Alexandre Jeannot, Emmanuel Swartvagher, Philippe Inria Bordeaux Sud Ouest Bordeaux France

ISBN: (纸本)9781665497473

To amortize the cost of MPI communications, distributed parallel HPC applications can overlap network communications with computations in the hope that it improves global application performance. When using this technique, both computations and communications are running at the same time. But computation usually also performs some data movements. Since data for computations and for communications use the same memory system, memory contention may occur when computations are memory-bound and large messages are transmitted through the network at the same time. In this paper we propose a model to predict memory band-width for computations and for communications when they are executed side by side, according to data locality and taking contention into account. Elaboration of the model allowed to better understand locations of bottleneck in the memory system and what are the strategies of the memory system in case of contention. the model was evaluated on many platforms with different characteristics, and showed a prediction error in average lower than 4 %.

关键词： HPC MPI Memory Contention NUMA Band-width Predictive Models Multicore processing

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An Empirical Performance Study of Chapel Programming Language

An Empirical Performance Study of Chapel Programming Languag...

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26th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Dun, Nan Taura, Kenjiro Univ Tokyo Bunkyo Ku Tokyo 1138656 Japan

ISBN: (纸本)9780769546766

In this paper we evaluate the performance of the Chapel programming language from the perspective of its language primitives and features, where the microbenchmarks are synthesized from our lessons learned in developing molecular dynamics simulation programs in Chapel. Experimental results show that most language building blocks have comparable performance to corresponding hand-written C code, while the complex applications can achieve up to 70% of the performance of C implementation. We identify several causes of overhead that can be further optimized by Chapel compiler. this work not only helps Chapel users understand the performance implication of using Chapel, but also provides useful feedbacks for Chapel developers to make a better compiler.

关键词： parallel languages performance evaluation

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Extremely Fast and Energy Efficient One-way Wave Equation Migration on GPU-based heterogeneous architecture 35

Extremely Fast and Energy Efficient One-way Wave Equation Mi...

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35th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Qu, Long Lucido, Loris Bonnasse-Gahot, Marie Vezolle, Pascal Klahr, Diego Total Pau France Eolen Pau France IBM Corp Montpellier France Total Houston TX USA

ISBN: (纸本)9781665440660

One-way Wave Equation Migration (OWEM) is a classic seismic imaging method offering a good trade-off between quality and compute cost in most geological cases. In recent years, GPU-based heterogeneous architecture has gained popularity for seismic imaging. In this paper, we present a generic design for asynchronous processing and data management. By applying this design, we present an efficient GPU implementation of OWEM combining OpenACC and CUDA. Our approach improves upon classic designs by exploring asynchronous compute and data transfer between CPU and GPU using high-speed NVLink, completely masking the cost of MPI communications and I/O. Using 3,018 GPUs, our tine-tuned OWEM can process 11,172 seismic shots in less than 75 minutes. By tuning CPU and GPU clock frequencies, we achieve around 30% energy saving with only 4% loss of performance on PANGEA III supercomputer. We believe our design combined with the energy-aware tuning will be beneficial to many GPU applications.

关键词： seismic imaging GPU accelerated computing parallel computing heterogeneous architecture energy-aware HPC

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Fault Modeling of Extreme Scale applications using Machine Learning 30

Fault Modeling of Extreme Scale Applications using Machine L...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Vishnu, Abhinav van Dam, Hubertus Tallent, Nathan R. Kerbyson, Darren J. Hoisie, Adolfy Pacific Northwest Natl Lab Richland WA 99352 USA Brookhaven Natl Lab Upton NY 11973 USA

ISBN: (纸本)9781509021406

Faults are commonplace in large scale systems. these systems experience a variety of faults such as transient, permanent and intermittent. Multi-bit faults are typically not corrected by the hardware resulting in an error. this paper attempts to answer an important question: Given a multi-bit fault in main memory, will it result in an application error and hence a recovery algorithm should be invoked - or can it be safely ignored? We propose an application fault modeling methodology to answer this question. Given a fault signature (a set of attributes comprising of system and application state), we use machine learning to create a model which predicts whether a multi-bit permanent/transient main memory fault will likely result in error. We present the design elements such as the fault injection methodology for covering important data structures, the application and system attributes which should be used for learning the model, the supervised learning algorithms (and potentially ensembles), and important metrics. We use three applications - NWChem, LULESH and SVM - as examples for demonstrating the effectiveness of the proposed fault modeling methodology.

关键词： applications Exascale Fault Machine Learning Modeling

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Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-based Multicores Executing parallel Data Analytics applications 32

Software-Hardware Managed Last-level Cache Allocation Scheme...

引用

27th international Heterogeneity in Computing Workshop in conjunction with 32nd IEEE international parallel and distributed processing symposium (IPDPS)

作者： Ahmad, Masab Dogan, Halit Checconi, Fabio Que, Xinyu Buono, Daniele Khan, Omer Univ Connecticut Storrs CT 06269 USA IBM Res Yorktown Hts NY 10598 USA

ISBN: (纸本)9781538643686

Developments in machine learning and graph analytics have seen these fields establish themselves as pervasive in a wide range of applications. Non-volatile memory (NVRAM) offers higher capacity and information retainment in case of power loss, therefore it is expected to be adopted for such applications. However, the asymmetric access latencies of NVRAM greatly degrade performance. the focus of this paper is to reduce the effect of memory access latency on emerging machine learning and graph workloads. the proposed mechanism uses software tagging of application data structures so as to control on-chip cache evictions based on data type and reuse patterns in an NVRAM based multicore system. Learner models are developed that are capable of predicting cache allocations for a variety of machine learning and graph applications. the optimized learning model yields an average performance benefit of 21% compared to a system that does not optimize for the write latency challenges in NVRAM.

关键词： Random access memory Nonvolatile memory Software Resource management Data structures Hardware Multicore processing"

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