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检索条件"任意字段=4th International Symposium on Parallel and Distributed Processing and Applications"

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A Semantic-aware Information System for Multi-Domain applications over Service Grids

A Semantic-aware Information System for Multi-Domain Applica...

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23rd IEEE international parallel and distributed processing symposium

作者： Comito, Carmela Mastroianni, Carlo Talia, Domenico Univ Calabria DEIS I-87030 Commenda Di Rende Italy CNR ICAR I-00185 Rome Italy

ISBN: (纸本)9781424437511

Service-oriented Grid frameworks offer resources and facilities to support the design and execution of distributed applications in different domains, ranging from scientific applications and public computing projects to commercial and industrial applications. A critical issue in such a context is the management Of the heterogeneity of resources and services offered by a Grid, including computers, data, and software tools provided by different organizations. this paper presents a general architecture of a service-oriented information system, which exploits the characteristics of a multi-domain and semantically enriched metadata model. the main objective of the information system is to uniformly manage service-oriented applications and basic resources by assuring metadata persistence through an XML distributed database, without merely relying on the functionalities of persistent Grid services. the information system has been implemented on the basic services of the WSRF-based Globus Toolkit 4 and its performance has been evaluated in a testbed.

关键词： Information systems

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ISPDC 2005 the 4th international symposium on parallel and distributed Computing

ISPDC 2005 The 4th International Symposium on Parallel and D...

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ISPDC 2005: 4th international symposium on parallel and distributed Computing

ISBN: (纸本)0769524346

the proceedings contain 45 papers. the topics discussed include: a new era in computing: moving services onto grid;new challenges in parallel organizations;cellular nonlinear network grids a new grid computing approach;towards scalable grid replica optimization framework;a comparative simulation analysis of P2P system architectures;adaptive window scheduling for a hierarchical agent system;enforcing consistency during the adaptation of a parallel component;a distributed algorithm for the maximum flow problem;towards Introducing code mobility on J2ME;a component-based software infrastructure for ubiquitous computing;service driven mobile Ad hoc networks formation and management;designing agent based travel support system;a study of meta-scheduling architectures for high throughput computing: pull versus push;scheduling scheme based on dedication rate in volunteer computing environment;and collaborative data distribution with BitTorrent for computational desktop grids.

关键词： parallel processing systems

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Hierarchical Local Storage: Exploiting Flexible User-Data Sharing Between MPI Tasks

Hierarchical Local Storage: Exploiting Flexible User-Data Sh...

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26th IEEE international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Tchiboukdjian, Marc Carribault, Patrick Perache, Marc Exascale Comp Res Versailles France

ISBN: (纸本)9780769546759

With the advent of the multicore era, the number of cores per computational node is increasing faster than the amount of memory. this diminishing memory to core ratio sometimes even prevents pure MPI applications to exploit all cores available on each node. A possible solution is to add a shared memory programming model like OpenMP inside the application to share variables between OpenMP threads that would otherwise be duplicated for each MPI task. Going to hybrid can thus improve the overall memory consumption, but may be a tedious task on large applications. To allow this data sharing without the overhead of mixing multiple programming models, we propose an MPI extension called Hierarchical Local Storage (HLS) that allows application developers to share common variables between MPI tasks on the same node. HLS is designed as a set of directives that preserve the original parallel semantics of the code and are compatible with C, C++ and Fortran languages and the OpenMP programming model. this new mechanism is implemented inside a state-of-the-art MPI 1.3 compliant runtime called MPC. Experiments show that the HLS mechanism can effectively reduce memory consumption of HPC applications. Moreover, by reducing data duplication in the shared cache of modern multicores, the HLS mechanism can also improve performances of memory intensive applications.

关键词： High Performance Computing parallel Programming Model Memory Consumption

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ARCHER: Effectively Spotting Data Races in Large OpenMP applications 30

ARCHER: Effectively Spotting Data Races in Large OpenMP Appl...

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30th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Atzeni, Simone Gopalakrishnan, Ganesh Rakamaric, Zvonimir Ahn, Dong H. Laguna, Ignacio Schulz, Martin Lee, Gregory L. Protze, Joachim Mueller, Matthias S. Mueller, Matthias S. Univ Utah Salt Lake City UT 84112 USA Lawrence Livermore Natl Lab Livermore CA USA Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9781509021406

OpenMP plays a growing role as a portable programming model to harness on-node parallelism;yet, existing data race checkers for OpenMP have high overheads and generate many false positives. In this paper, we propose the first OpenMP data race checker, ARCHER, that achieves high accuracy, low overheads on large applications, and portability. ARCHER incorporates scalable happens-before tracking, exploits structured parallelism via combined static and dynamic analysis, and modularly interfaces with OpenMP runtimes. ARCHER significantly outperforms TSan and Intel (R) Inspector XE, while providing the same or better precision. It has helped detect critical data races in the Hypre library that is central to many projects at Lawrence Livermore National Laboratory and elsewhere.

关键词： data race detection OpenMP high performance computing static analysis dynamic analysis

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An Efficient Racetrack Memory-Based processing-In-Memory Architecture for Convolutional Neural Networks 15

An Efficient Racetrack Memory-Based Processing-In-Memory Arc...

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15th IEEE international symposium on parallel and distributed processing with applications (ISPA) / 16th IEEE international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Liu, Bicheng Gu, Shouzhen Chen, Mingsong Kang, Wang Hu, Jingtong Zhuge, Qingfeng Sha, Edwin H-M East China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai Peoples R China Beihang Univ Fert Beijing Inst BDBC Beijing Peoples R China Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA USA Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781538637906

As a promising architectural paradigm for applications which demand high I/O bandwidth, processing-in-Memory (PIM) computing techniques have been adopted in designing Convolutional Neural Networks (CNNs). However, due to the notorious memory wall problem, PIM based on existing device memory still cannot deal with complex CNN applications under the constraints of memory bandwidth and processing latency. To mitigate this problem, this paper proposes an efficient PIM architecture based on skyrmion and domain-wall racetrack memories, which can further exploit the potential of PIM architectures in terms of processing latency and energy efficiency. By adopting full adders and multipliers developed using skyrmion and domain-wall nanowires, our proposed PIM architecture can accommodate complex CNNs at different scales. Experimental results show that comparing with both traditional and state-of-the-art PIM architectures, our proposed PIM architecture can improve the processing latency and energy efficiency of CNNs drastically.

关键词： Logic gates Micromagnetics Nanowires Random access memory Memory management Adders

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Input-parallel Output-Series isolated DC-DC Converter for PV Generation System

Input-Parallel Output-Series isolated DC-DC Converter for PV...

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4th IEEE international symposium on Power Electronics for distributed Generation Systems (PEDG)

作者： Gu, Ling Kong, Yueping Jin, Ke Shen, Zhiyuan Nanjing Univ Aeronaut & Astronaut Jiangsu Key Lab New Energy Generat & Power Conver Nanjing 210016 Jiangsu Peoples R China

ISBN: (纸本)9781479906925

the topology of photovoltaic (PV) power system is categorized on the basis of number of power processing stages. the single-stage dc-dc converter has the advantage of simple structure and high efficiency, however it must handle all tasks itself, i.e., maximum power point tracking and, perhaps, voltage amplification. Instead, the control system of the dual-stage dc-dc converter is simple but its complex structure affects its efficiency. Also the architecture of the PV power systems also affects the efficiency greatly. So in this paper, a new architecture with an input-parallel-output-series isolated dc-dc converter is proposed. In this architecture, most of the PV power is directly transferred to the DC bus through the dc transformer and the voltage difference between the PV string and the fixed DC bus is compensated by a power compensator. thus, a high efficiency can be reached. A 1 kW prototype is built and tested in the lab. the experimental results are presented to verify the validation of the effectiveness of the proposed PV architecture.

关键词： Photovoltaic power system Power compensating Input-parallel output-series Small signal modeling self-driven

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SPHYNX: Spectral Partitioning for HYbrid aNd aXelerator-enabled systems 34

SPHYNX: Spectral Partitioning for HYbrid aNd aXelerator-enab...

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34th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Acer, Seher Boman, Erik G. Rajamanickam, Sivasankaran Sandia Natl Labs Ctr Comp Res POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781728174457

Graph partitioning has been an important tool to partition the work among several processors to minimize the communication cost and balance the workload. While accelerator-based supercomputers are emerging to be the standard, the use of graph partitioning becomes even more important as applications are rapidly moving to these architectures. However, there is no scalable, distributed-memory, multi-GPU graph partitioner available for applications. We developed a spectral graph partitioner, Sphynx, using the portable, accelerator-friendly stack of the Trilinos framework. We use Sphnyx to systematically evaluate the various algorithmic choices in spectral partitioning with a focus on GPU performance. We perform those evaluations on irregular graphs, because state-of-the-art partitioners have the most difficulty on them. We demonstrate that Sphynx is up to 17x faster on GPUs compared to the case on CPUs, and up to 580x faster compared to a state-of-the-art multilevel partitioner. Sphynx provides a robust alternative for applications looking for a GPU-based partitioner.

关键词： graph partitioning spectral partitioning GPUs distributed-memory systems

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Performance Impact of Batching Web-Application Requests Using Hot-spot processing on GPUs 29

Performance Impact of Batching Web-Application Requests Usin...

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29th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Fjalling, Tobias Stenstrom, Per Admeta WideOrbit Gothenburg Sweden Chalmers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781479986484

Web applications are a good fit for many-core servers because of their inherent high-degree of request-level parallelism. Yet, processing-intensive web-server requests can lead to low quality-of-service due to hot-spots, which calls for methods that can improve single-thread performance. this paper explores how to use off-chip GPUs to speed up web application hot-spots written in productivity-friendly environments (e.g. C#). First, we apply a number of straightforward optimizations through refactoring of a commercial-strength, web application code. this yields a speedup of 7.6 in a CPU multi-threaded, and multi-core test. Second, we then gather similar requests from different threads of the optimized code, by applying a technique called batching, to exploit SIMD parallelism provided by GPUs. Surprisingly, there is ample parallelism to be exploited from the already optimized code yielding a speedup of a factor between 2x to 3x compared to the best optimized CPU version.

关键词： GPU batching high-throughput web server web applications Speeding BATCHES GRAPPER PICK UP parallelism Synclitism Graphics processing Unit Online resources Hot spots Codes central processing units

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A Hybrid Scheduling Scheme for parallel Loops 35

A Hybrid Scheduling Scheme for Parallel Loops

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35th IEEE international parallel and distributed processing symposium (IPDPS)

作者： Handleman, Aaron Rattew, Arthur G. Lee, I-Ting Angelina Schardl, Tao B. Washington Univ St Louis MO 14263 USA MIT Cambridge MA 02139 USA Univ Oxford Oxford England

ISBN: (纸本)9781665440660

parallel loops are commonly used parallel constructs to parallelize high-performance scientific applications. In the paradigm of task parallelism, the parallel loop construct is used to express the logical parallelism of the loop, indicating that the iterations in a loop are logically in parallel and let an underlying runtime scheduler determines how to best map the parallel iterations onto available processing cores. Researchers have investigated multiple scheduling schemes for scheduling parallel loops, with the static partitioning and dynamic partitioning being most prevalent. Static partitioning obtains low scheduling overhead while potentially retaining locality benefit in iterative applications that perform a sequence of parallel loops that access the same set of data repeatedly. But static partitioning may perform poorly relatively to dynamic partitioning if the loop iterations contain unbalanced workloads or if the cores can arrive at the loops in different times. We propose a hybrid scheduling scheme, which first schedules loops using static partitioning but then employs dynamic partitioning when load balancing is necessary. Moreover, the work distribution employs a claiming heuristic that allows a core to check for partitions to work on in a semi-deterministic fashion, allowing the scheduling to better retain data locality in the case of iterative applications. Unlike prior work that optimizes for iterative applications, our scheme does not require programmer annotations and can provide provably efficient execution lime. In this paper, we discuss the hybrid scheme, prove its correctness, and analyze its scheduling bound. We have also implemented the proposed scheme in a Cilk-based work-stealing platform and experimentally verified that the scheme load balances well and can retain locality for such iterative applications.

关键词： static partitioning dyantnic partitioning work stealing work span

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Communication-efficient Massively distributed Connected Components 36

Communication-efficient Massively Distributed Connected Comp...

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36th IEEE international parallel and distributed processing symposium (IEEE IPDPS)

作者： Lamm, Sebastian Sanders, Peter Karlsruhe Inst Technol Inst Theoret Informat Karlsruhe Germany

ISBN: (纸本)9781665481069

Finding the connected components of an undirected graph is one of the most fundamental graph problems. Connected components are used in a wide spectrum of applications including VLSI design, machine learning and image analysis. Sequentially, one can easily find all connected components in linear time using breadth-first traversal. However, in a massively distributed setting, finding connected components in a scalable way becomes much harder due to data irregularities and the overhead associated with the increased need for communication. In this work, we present a communication-efficient distributed graph algorithm for finding connected components that scales to massively parallel machines. Our algorithm is based on a recent linear-work shared-memory parallel algorithm by Blelloch et al. [1] and refines it for a distributed memory setting. this includes a communication-efficient graph contraction procedure, as well as a distributed variant of the low diameter decomposition by Miller et al. [2]. We tackle the data irregularities introduced by high degree vertices by using an efficient procedure for distributing their incident edges. Our experimental evaluation on up to 16 384 cores indicates a good weak scaling behavior that outperforms current state-of-the-art algorithms.

关键词： graph algorithms distributed algorithms communication efficiency graph connectivity

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