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international symposium on parallel processing

作者： S. Goil A. Choudhary Department of Electrical & Computer Engineering Technological Institute Northwestern University Evanston IL USA

Multidimensional Analysis and On-Line Analytical processing (OLAP) uses summary information that requires aggregate operations along one or more dimensions of numerical data values. Query processing for these applications require different views of data for decision support. the Data Cube operator provides multi-dimensional aggregates, used to calculate and store summary information on a number of dimensions. the multi-dimensionality of the underlying problem can be represented both in relational and multi-dimensional databases, the latter being a better fit when query performance is the criteria for judgment. Relational databases are scalable in size and efforts are on to make their performance acceptable. On the other hand multi-dimensional databases perform well for such queries, although they are nor very scalable. parallel computing is necessary to address the scalability and performance issues for these data sets. In this paper we present a parallel and scalable infrastructure for OLAP and multidimensional analysis. We use chunking to store data either as a dense block using multidimensional arrays (md-arrays) or a sparse set using a Bit encoded sparse structure (BESS). Chunks provide a multidimensional index structure for efficient dimension oriented data accesses much the same as md-arrays do. Operations within chunks and between chunks are a combination of relational and multi-dimensional operations depending on whether the chunk is sparse or dense. We present performance results for data sets with 3, 5 and 10 dimensions for our implementation on the IBM SP-2 which show good speedup and scalability.

关键词： Multidimensional systems Databases Data structures Aggregates Information analysis Decision support systems Data mining Performance analysis

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Techniques for automating distributed real-time applications design

Techniques for automating distributed real-time applications...

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international symposium on High Performance distributed Computing

作者： Dong-In Kang R. Gerber L. Golubchik J.K. Hollingsworth Department of Computer Science & WACS University of Maryland College Park MD USA

Presents a performance-based methodology for designing a high-bandwidth radar application on commodity platforms. Unlike many real-time systems, our approach works for commodity processors running commodity operating systems. Our technique is innovative because it uses stochastic models of the processing time at each step in the process to allow for the variabilities of running on a non-real-time operating system. We show how our system synthesizes the runtime parameters for a synthetic aperture radar application under a variety of loading conditions.

关键词： Delay Synthetic aperture radar Radar applications throughput parallel processing Radar imaging Fault tolerance Redundancy Fault tolerant systems Algorithm design and analysis

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Impact of memory hierarchies on cluster computing

Proceedings of the International Parallel Processing Symposi...

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Proceedings of the international parallel processing symposium, IPPS 1999年 61-69页

作者： Du, King Zhang, Xiaodong Univ of Virginia Charlottesville United States

Using off-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform for a given budget and for certain types of application workloads is mainly determined by its memory hierarchy and interconnection network of the cluster. Finding such a solution from exhaustive simulations would be highly time-consuming and expensive;and predictions from measurements on existing clusters would be impractical. We present an analytical model for evaluating performance impact of memory hierarchies and networks on cluster computing. the model covers the memory hierarchy of a single SMP, a cluster of workstations/PCs, or a cluster of SMPs by changing various modeling and architectural parameters. Network variations covering bus and switch networks are also included in the analysis. applications of different types are characterized by parameterized workloads with different computation and communication requirements. the model has been validated by simulations. Our study shows that the length of memory hierarchy is the most sensitive factor to affect the execution time for many types of workloads. However, the interconnection network cost of a tightly coupled system with a short length of memory hierarchy, such as an SMP is significantly more expensive than a normal cluster network connecting independent computer nodes. thus, the essential issue to be considered is the trade-off between the length of memory hierarchy and system cost. Based on analytical and case studies, we present our quantitative recommendations for building cost-effective clusters for different application workloads.

关键词： parallel processing systems

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Randomized initialization protocols for packet radio networks

Proceedings of the International Parallel Processing Symposi...

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Proceedings of the international parallel processing symposium, IPPS 1999年 544-548页

作者： Hayashi, Tatsuya Nakano, Koji Olariu, Stephan Nagoya Inst of Technology Nagoya Japan

the main contribution of this work is to propose efficient randomized leader election and initialization protocols for Packet Radio Networks (PRN, for short). As a result of the initialization protocol, the n stations of a PRN are assigned distinct integer IDs from 1 to n. the results include protocols to: (1) initialize the single-channel PRN with the collision detection (CD) capability in O(n) rounds with probability at least 1-1/2n;(2) initialize the k-channel PRN with CD capability in O(n/k) rounds with probability at least 1-1/n, whenever k&len/3 log n;(3) elect a leader on the single-channel PRN with no CD in O((log n)2) broadcast rounds with probability at least 1-1/n;(4) initialize the single-channel PRN with no CD in O(n) rounds with probability at least 1-1/2√n;(5) initialize the k-channel PRN with no CD in O(n/k) broadcast rounds with probability at least 1-1/n, whenever k&len/4(log n)2.

关键词： parallel processing systems

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the impact of memory hierarchies on cluster computing

The impact of memory hierarchies on cluster computing

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international symposium on parallel processing

作者： Xing Du Xiaodong Zhang Department of Computer Science University of Virginia Charlottesville VA USA Department of Computer Science College of William and Mary Williamsburg VA USA

ISBN: (纸本)0769501435

Using of-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform for a given budget and for certain types of application workloads is mainly determined by its memory hierarchy and interconnection network of the cluster. Finding such a solution from exhaustive simulations would be highly time-consuming and expensive; and predictions from measurements on existing clusters would be impractical. We present an analytical model for evaluating performance impact of memory hierarchies and networks on cluster computing. the model covers the memory hierarchy of a single SMP, a cluster of workstations/PCs, or a cluster of SMPs by changing various modeling and architectural parameters. Network variations covering bus and switch networks are also included in the analysis. applications of different types are characterized by parameterized workloads with different computation and communication requirements. the model has been validated by simulations. Our study shows that the length of memory hierarchy is the most sensitive factor to affect the execution time for many types of workloads. However, the interconnection network cost of a tightly coupled system with a short length of memory hierarchy, such as an SMP is significantly more expensive than a normal cluster network connecting independent computer nodes. thus, the essential issue to be considered is the trade-off between the length of memory hierarchy and system cost. Based on analytical and case studies, we present our quantitative recommendations for building cost-effective clusters for different application workloads.

关键词： Computer networks Workstations Personal communication networks Multiprocessor interconnection networks Computational modeling Switches Costs parallel processing Predictive models Analytical models

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MPI code encapsulating using parallel CORBA object

MPI code encapsulating using parallel CORBA object

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international symposium on High Performance distributed Computing

作者： C. Rene T. Priol IRISA/IFSIC Rennes France IRISA/INRIA Rennes France

this paper describes a technique that allows an MPI code to be encapsulated into a component. Our technique is based on an extension to the Common Object Request Broker Architecture (CORBA) from the OMG (Object Management Group). the proposed extensions do not modify the CORBA core infrastructure (the Object Request Broker) so that it can fully co-exist with existing CORBA applications. An MPI code is seen as a new kind of CORBA object that hides most of the cumbersome problems when dealing with parallelism. Such technique can be used to connect MPI codes to existing CORBA software infrastructures which are now being developed in the framework of several research and development projects such as JACO3, JULIUS or TENT from DLR. To illustrate the concept of parallel CORBA object, we present a virtual reality application that is made of the coupling of a light simulation application (radiosity) and a visualisation tool using VRML and Java.

关键词： Computational modeling parallel processing Application software Computer simulation Numerical simulation Middleware distributed processing Concurrent computing Iris Research and development

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distributed, scalable, dependable real-time systems: middleware services and applications

Distributed, scalable, dependable real-time systems: middlew...

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international symposium on parallel processing

作者： L.R. Welch B. Ravindran P.V. Werne M.W. Masters B.A. Shirazi P.A. Shirolkar R.D. Harrison W. Mills Tuy Do J. Lafratta S.M. Anwar S. Sharp T. Sergeant G. Bilowus M. Swick J. Hoppel J. Caruso Computer Science & Engineering Department University of Texas Arlington Arlington TX USA The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA Code B35 Naval Surface Warfare Center Dahlgren VA USA Computer Science Corporation Dahlgren VA USA Ouachita Baptist University Arkadelphia AR USA

Some classes of real-time systems function in environments which cannot be modeled with static approaches. In such environments, the arrival rates of events which drive transient computations may be unknown. Also, the periodic computations may be required to process varying numbers of data elements per period, but the number of data elements to be processed in an arbitrary period cannot be known at the time of system engineering, nor can an upper bound be determined for the number of data items; thus, a worst case execution time cannot be obtained for such periodics. this paper presents middleware services that support such dynamic real-time systems through adaptive resource management. the middleware services have been implemented and employed for components of the experimental Navy system described by L.R. Welch et al. (1996). Experimental characterizations show that the services provide timely responses, that they have a low degree of intrusiveness on hardware resources, and that they are scalable.

关键词： Real time systems Middleware Resource management Scalability Load management Computer science Military computing Data engineering Systems engineering and theory Upper bound

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An efficient VLSI architecture parallel prefix counting with domino logic

An efficient VLSI architecture parallel prefix counting with...

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international symposium on parallel processing

作者： Rong Lin K. Nakano S. Olariu A.Y. Zomaya Department of Computer Science SUNY at Geneseo Geneseo NY USA Department of Electrical and Computer Engineering Nagoya Institute of Technology Nagoya Japan Department of Computer Science Old Dominion University Norfolk VA USA Department of Electrical and Electronic Engineering Perth WA Australia

We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores results in a network that is fast and highly hardware-compact. the proposed architecture for prefix counting N-1 bits features a total delay of (4 log N+/spl radic/N-2)*T/sub d/, where T/sub d/ is the delay for charging or discharging a row of two prefix sum units of eight shift switches. Simulation results reveal that T/sub d/ does not exceed Ins under 0.8-micron CMOS technology. Our design is faster than any design known to us for N/spl les/2/sup 10/ Yet another important and novel feature of the proposed architecture is that it requires very simple controls, partially driven by semaphores, reducing significantly the hardware complexity and fully utilizing the inherent speed of the process.

关键词： Very large scale integration Switches Signal processing CMOS technology Delay Signal design Logic design Digital arithmetic Computer architecture Concurrent computing

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A parallel algorithm for bound-smoothing

A parallel algorithm for bound-smoothing

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international symposium on parallel processing

作者： K. Rajan N. Deo Department of Computer Science University of Central Florida Orlando FL USA

Determining molecular structure from interatomic distances is an important and challenging problem. Given a molecule with n atoms, lower and upper bounds on interatomic distances can usually be obtained only for a small subset of the n(n-1)/2 atom pairs, using NMR. Given the bounds so obtained on the distances between some of the atom pairs, it is often useful to compute tight bounds on all the n(n-1)/2 pairwise distances. this process is referred to as bound-smoothing. the initial lower and upper bounds for the pairwise distances not measured are usually assumed to be 0 and /spl infin/. One method for bound-smoothing is to use the limits imposed by the triangle inequality. the distance bounds so obtained can often be tightened further by applying the tetrangle inequality-the limits imposed on the six pairwise distances among a set of four atoms (instead of three for the triangle inequalities). the tetrangle inequality is expressed by the Cayley-Menger determinants. For every quadruple of atoms, each pass of the tetrangle-inequality bound-smoothing procedure finds upper and lower limits on each of the six distances in the quadruple. Applying the tetrangle inequalities to each of the (/sub 4//sup n/) quadruples requires /spl theta/(n/sup 4/) time. Here, we propose a parallel algorithm for bound-smoothing employing the tetrangle inequality. Each pass of our algorithm requires /spl theta/(n/sup 3/ log n) time on a CREW PRAM with /spl theta/(n/log n) processors. An implementation of this parallel algorithm on the Intel Paragon XP/S and its performance are also discussed.

关键词： parallel algorithms Upper bound Geometry Computer science Nuclear magnetic resonance Atomic measurements Phase change random access memory Euclidean distance Computational biology Polynomials

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parallel biological sequence comparison using prefix computations

Proceedings of the International Parallel Processing Symposi...

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Proceedings of the international parallel processing symposium, IPPS 1999年 653-659页

作者： Aluru, Srinivas Futamura, Natsuhiko Mehrotra, Kishan New Mexico State Univ Las Cruces United States

We present practical parallel algorithms using prefix computations for various problems that arise in pairwise comparison of biological sequences. We consider both constant and affine gap penalty functions, full-sequence and subsequence matching, and space-saving algorithms. the best known sequential algorithms solve these problems in O(mn) time and O(m+n) space, where m and n are the lengths of the two sequences. All the algorithms presented in this paper are time optimal with respect to the best known sequential algorithms and can use O (n/log n) processors where n is the length of the larger sequence. While optimal parallel algorithms for many of these problems are known, we use a simple framework and demonstrate how these problems can be solved systematically using repeated parallel prefix operations. We also present a space-saving algorithm that uses O (m+n/p) space and runs in optimal time where p is the number of the processors used.

关键词： parallel algorithms

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