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Sorting N items using a p-sorter in optimal time

Sorting N items using a p-sorter in optimal time

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international symposium on parallel and distributed processing (IPDPS)

作者： S. Olarin S.Q. Zheng Dept. of Comput. Sci. Old Dominion Univ. Norfolk VA USA Department of Computer Science Louisiana State University Baton Rouge LA USA

A sorting device capable of sorting p items in constant time is called a p-sorter. It is known that the task of sorting N items using a p-sorter requires at least /spl Omega/ (N log N/p log p) applications of the p-sorter. this bound is tight: there exist algorithms that use O (N log N/p log p) calls to the p-sorter to sort N items. However, there is no known implementable algorithm that can sort N items in O(N log N/p log p) time using a p-sorter. the main contribution of this paper is to propose a simple VLSI architecture and to show that in our architecture N items can be sorted in O(N log N/p log p) calls to the p-sorter, while enforcing conflict-free memory accesses. An important feature of our design is that the total additional VLSI area for hardware, other than the memory for data and the p-sorter, is kept to a minimum.

关键词： Sorting Very large scale integration Computer architecture Computer science Semiconductor device measurement Application software Hardware parallel algorithms parallel processing parallel architectures

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distributed simulation of parallel executions

Distributed simulation of parallel executions

引用

Annual symposium on Simulation

作者： L. Ricciulli P. Lincoln J. Meseguer Computer Science Laboratory SRI International Inc. Menlo Park CA USA

We propose a new practical technique for the distributed execution-driven simulation of parallel computers. Our simulation methodology allows complete verbalization of the design at all levels and achieves good performance by preserving and exploiting the parallelism of the parallel program being simulated. With our technique it is possible to decouple the simulation of the execution of a parallel application from the estimation of the virtual execution time in which such execution is carried out. Our technique uses minimal overhead to maintain coherent distributed event causality relations by making it possible for the simulated executions to reflect the intrinsic uncertainties of parallel applications being simulated. We include a detailed description of our methodology, explain how to apply our ideas to parallelize an existing execution-driven sequential simulator under quite general assumptions, discuss the trade-offs of our methodology, and give preliminary performance measurements of a distributed simulator that uses our technique.

关键词： Computational modeling distributed computing Discrete event simulation High performance computing Testing Computer science Laboratories Computer simulation Concurrent computing parallel processing

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Efficient algorithms for block-cyclic redistribution of arrays

Efficient algorithms for block-cyclic redistribution of arra...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Young Won Lim P.B. Bhat V.K. Prasanna Department of EE-Systems University of Southern California Los Angeles CA USA

We present new algorithmic techniques for a classical research problem, runtime redistribution of an array from one block-cyclic layout to another. Our methodology for reducing communication overheads is based on a generalized circulant matrix formalism. Using this formalism, we derive direct, indirect, and hybrid communication schedules for the cyclic redistribution problem when the block size changes by an integer factor K. We have also developed formulae to estimate the timing performance of each of these schedules for a given parallel machine and redistribution problem. In our indirect communication schedule, blocks are moved from a source processor to a destination processor through intermediate "relay" processors. this reduces the number of communication steps by an order of magnitude, in comparison with previous approaches. this algorithm performs cyclic(x) to cyclic(Kx) redistribution on P processors in [log/sub 2/K]+2 steps. Implementations of these algorithms on the Cray T3D and on the IBM SP-2 show superior performance over previous approaches. Since our algorithms are developed using MPI, they can be easily ported to different application environments. Our techniques can be used in the design of scalable redistribution libraries, in efficient implementations of the REDISTRIBUTE directive of HPF and in developing parallel algorithms for various HPC applications.

关键词： Signal processing algorithms Processor scheduling parallel machines Algorithm design and analysis Libraries parallel algorithms High performance computing Program processors Programming profession Search problems

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A unified algorithm for blind separation of independent sources

A unified algorithm for blind separation of independent sour...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Je Zhu Xi-Ren Cao M.L. Liou Department of Electrical & Electronic Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

this paper presents a unified algorithm of blind source separation based on the "Independent Component Analysis"(ICA) principle. the algorithm can separate all sources provided there is at most one Gaussian distributed source. the key point is to find a matrix by which the estimates of the original signals are pairwise independent in the absence of noises. If the observed signals are corrupted by noises, minimum-variance unbiased estimates are obtained. In comparison with the algorithm proposed previously by the authors, this algorithm has a parallel pipeline structure, and will not need a preset threshold if both of the 3rd- and 4th-order cumulants of any non-Gaussian distributed source are not zero. this algorithm has significant advantages over existing algorithms.

关键词： Blind source separation Signal processing algorithms Independent component analysis Vectors Matrix decomposition Water resources Algorithm design and analysis Sensor phenomena and characterization Noise cancellation Image enhancement

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distributed list coloring: how to dynamically allocate frequencies to mobile base stations

Distributed list coloring: how to dynamically allocate frequ...

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international symposium on parallel and distributed processing (IPDPS)

作者： N. Garg M. Papatriantafilou P. Tsigas Max Planck Institute of Computer Science Saarbrucken Germany

To avoid signal interference in mobile communication it is necessary that the channels used by base stations for broadcast communication within their cells are chosen so that the same channel is never concurrently used by two neighboring stations. We model this channel allocation problem as a generalized list coloring problem and we provide two distributed solutions which are also able to cope with crash failures by limiting the size of the network affected by a faulty station in terms of the distance from that station. Our first solution uses a powerful synchronization mechanism to achieve a response time that depends only on /spl Delta/, the maximum degree of the signal interference graph, and a failure locality of 4. Our second solution is a simple randomized solution in which each node can expect to pick f/(4/spl Delta/) colors where f is the size of the list at the node; the response time of this solution is a constant and the failure locality 1. Besides being efficient (their complexity measures involve only small constants), the protocols presented in this work are simple and easy to apply in practice, provided the existence of distributed infrastructure in networks that are in use.

关键词： Radio spectrum management Interference Mobile communication Delay Base stations Broadcasting Channel allocation Computer crashes Frequency synchronization Protocols

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Scheduling from the perspective of the application 96

Scheduling from the perspective of the application

引用

international symposium on High Performance distributed Computing

作者： F. Berman R. Wolski Department of Computer Science and Engineering University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA US Dept. of Comput. Sci. & Eng. California Univ. San Diego La Jolla CA USA

ISBN: (纸本)9780818675829

Metacomputing is the aggregation of distributed and high-performance resources on coordinated networks. With careful scheduling, resource-intensive applications can be implemented efficiently on metacomputing systems at the sizes of interest to developers and users. In this paper, we focus on the problem of scheduling applications on metacomputing systems. We introduce the concept of application-centric scheduling in which everything about the system is evaluated in terms of its impact on the application. Application-centric scheduling is used by virtually all metacomputer programmers to achieve performance on metacomputing systems. We describe two successful metacomputing applications to illustrate this approach, and describe AppLeS (Application-Level Scheduling) agents which generalize the application-centric scheduling approach. Finally, we show preliminary results which compare AppLeS-derived schedules with conventional strip and blocked schedules for a 2D Jacobi code.

关键词： Metacomputing Processor scheduling Concurrent computing Application software parallel processing High performance computing Strips Jacobian matrices Computer networks Contracts

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the active-ray approach to rendering on distributed memory multiprocessors

The active-ray approach to rendering on distributed memory m...

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international symposium on parallel and distributed processing (IPDPS)

作者： A. Law R. Yagel Department of Computer and Information Science Ohio State Uinversity USA

Object dataflow is a popular approach used in parallel rendering. the data representing the 3D scene is statically distributed among processors and objects are fetched and cached only on demand. Most previous object dataflow methods were implemented on shared memory architectures and exploited spatial coherency to reduce hardware cache misses. We propose an efficient model for object dataflow parallel volume rendering on message passing machines. the active ray tracing algorithm is introduced and its ray storage mechanism is used to support latency hiding by postponing computation on inactive rays. Memory usage is optimized by letting objects migrate and replicate at different processors rather than the common static assignments. Our cache-only-memory approach uses a distributed-directory scheme to trace the location of objects at other nodes. A mechanism to minimize network congestion was implemented which optimizes channel utilization. Unlike previous methods, our approach can benefit from temporal coherence and effectively minimizes communication costs in successive frames. We implemented a volume ray casting instance of the algorithm on the Cray T3D and achieved higher efficiency and scalability than existing algorithms. We achieve interactive frame rates of approximately 20 Hz for 128/sup 3/ volume, and 4 Hz for 256/sup 3/ volume on 128 processors.

关键词： Layout Memory architecture Spatial coherence Hardware Message passing Ray tracing Delay Costs Casting Scalability

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Performance comparison of desktop multiprocessing and workstation cluster computing 96

Performance comparison of desktop multiprocessing and workst...

引用

international symposium on High Performance distributed Computing

作者： P.E. Crandall E.V. Sumithasri M.A. Clement Computer Science & Engineering University of Connecticut Storrs CT USA Computer Science Department Brigham Young University Provo UT USA

ISBN: (纸本)9780818675829

the paper describes initial findings regarding the performance tradeoffs between cluster computing where the participating processors are independent machines connected by a high speed switch and desktop multiprocessing where the processors reside within a single workstation and share a common memory. While interprocessor communication time has typically been cited as the limiting force on performance in the cluster, bus and memory contention have had similar effects in shared memory systems. the advent of high speed interconnects and improved bus and memory access speeds have enhanced the performance curves of both platforms. We present comparisons of the execution times of three applications with varying levels of data dependencies-numerical integration, matrix multiplication, and Jacobi iteration across three environments: the PVM distributed memory model, the PVM shared memory model, and the Solaris threads package.

关键词： Workstations Switches parallel processing Computer science High performance computing Communication switching Jacobian matrices Concurrent computing distributed computing Costs

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I/O requirements of scientific applications: an evolutionary view 96

I/O requirements of scientific applications: an evolutionary...

引用

international symposium on High Performance distributed Computing

作者： E. Smirni R.A. Aydt A.A. Chien D.A. Reed Department of Computer Science University of Illinois Urbana IL USA

ISBN: (纸本)9780818675829

the modest I/O configurations and file system limitations of many current high-performance systems preclude solution of problems with large I/O needs. I/O hardware and file system parallelism is the key to achieving high performance. We analyze the I/O behavior of several versions of two scientific applications on the Intel Paragon XP/S. the versions involve incremental application code enhancements across multiple releases of the operating system. Studying the evolution of I/O access patterns underscores the interplay between application access patterns and file system features. Our results show that both small and large request sizes are common, that at present, application developers must manually aggregate small requests to obtain high disk transfer rates, that concurrent file accesses are frequent, and that appropriate matching of the application access pattern and the file system access mode can significantly increase application I/O performance. Based on these results, we describe a set of file system design principles.

关键词： Hardware File systems parallel processing Application software Contracts Computer science Operating systems Aggregates Pattern matching Software performance

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A new design approach and VLSI implementations of recursive digital filters

A new design approach and VLSI implementations of recursive ...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Yin-Tsung Hwang Ching-Long Sue Department of Electronic Engineering National Yunlin Institute of Technology Yunlin Taiwan

In this paper we address the design problem of high speed recursive digital filters for real time applications. In contrast to the nonrecursive case, there exist feedback loops in recursive filters which often become the performance bottleneck and prevent the circuits from high speed operation. Design tactics such as pipelining and parallel processing offer little help in this case. To achieve more parallelism, a look-ahead transformation applied at the algorithm level may be employed. this however, often causes a drastic increase in the hardware complexity. In this paper we propose a new design approach based on distributed Arithmetic (DA) for the recursive filters. It can outperform the traditional bit parallel design in both pipelining period and initiation interval. To illustrate this new approach, we present 2 different systolic array designs for the ARMA filter. Finally, both designs are implemented by 0.8 /spl mu/m SPDM CMOS technology. For the 4-tap 8-bit wide designs, the simulation results show they can operate at 142.6 and 142.8 MHz, respectively.

关键词： Very large scale integration Pipeline processing CMOS technology Digital filters Feedback loop Feedback circuits parallel processing Hardware Arithmetic Systolic arrays

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