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design and implementation of Multi-Purpose DCT/DST-Specific Accelerator on Heterogeneous Multicore Architecture 4

Design and Implementation of Multi-Purpose DCT/DST-Specific ...

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4th IEEE Nordic Circuits and systems Conference (NORCAS) / NORCHIP and International symposium of system-on-Chip (SoC)

作者： Nouri, Sajjad Ghaznavi-Youvalari, Ramin Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn Tampere Finland Nokia Technol Espoo Finland

ISBN: (纸本)9781538676561

this paper presents the implementation of various sizes of Discrete Cosine transform (DCT) and Discrete Sine Transform (DST) dedicated for High Efficiency Video Coding (HEVC) standard by using template-based Coarse-Grained Reconfigurable Arrays (CGRAs) as accelerators on Heterogeneous Accelerator-Rich Platform (HARP). the proposal makes multipurpose DCT/DST specific accelerators in such a way that final architecture consists of 4/8/16/32-point DCT and 4-point DST. the accelerators are primarily designed by crafting template-based CGRA devices at different dimensions and then arranging them on a Network-on-Chip platform along with a few RISC cores. In this research work, the performance of each DCT/DST-specific accelerator, the collective performance of the whole platform and the NoC traffic are recorded in terms of the number of clock cycles and several high-level performance metrics. Conducted experiments show that 4-point DCT and 4-point DST can be implemented completely in 54 and 56 clock cycles, respectively, while for 8/16/32-point DCT, 67, 179 and 354 clock cycles are required, respectively. the achieved total power dissipation and energy consumption based on post placement and routing information are equal to 4.1 W and 10.87 mu J, respectively with 256 instantiated Processing Elements (PEs) at 200.0 MHz operating frequency. It resulted to a performance of 51.2 Giga Operations Per Second (GOPS) and 12 MOPS/mW as an architectural constant for the HARP template on 28 nm Altera Stratix-V chip. the proposed architecture is able to sustain Full HD 1080p format at 30 fps on FPGA.

关键词： Reconfigurable CGRA Network-on-Chip Heterogeneous Accelerator Multicore DCT DST HEVC

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design and implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture 4

Design and Implementation of 2D IDCT/IDST-Specific Accelerat...

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4th IEEE Nordic Circuits and systems Conference (NORCAS) / NORCHIP and International symposium of system-on-Chip (SoC)

作者： Pourabed, Mohammad Ali Nouri, Sajjad Nurmi, Jari Tampere Univ Technol Lab Elect & Commun Engn POB 553 FI-33101 Tampere Finland

ISBN: (纸本)9781538676561

the paper talks about how to implement different sizes of Inverse Discrete Cosine Transform (IDCT) as well as Inverse Discrete Sine transform (IDST) that are dedicated on High Efficiency Video Coding (HEVC) standard through employing Coarse-Grained Reconfigurable Arrays (CGRAs) as a template-based accelerators on Heterogeneous Accelerator-Rich Platform (HARP). the proposal designs multi-purpose IDCT/IDST-based accelerators in a manner that the final architecture is made up of 4-point IDST and 4/8-point IDCT. the designing of the accelerators is done by creating template-based CGRA devices at various dimensions after which they are arranged in a sequential manner over a structure that is Network-on-Chip (NoC) based accompanied by a number of RISC cores. the research records the IDCT/IDST-specific accelerator performance, the entire platform's performance, as well as the traffic of the NoC with regard to the total number of clock cycles made as well as several other high-level metrics of performance. the experiments that were conducted found that 4-point IDCT and 4-point IDST can be totally implemented in 56 clock cycles. For 8-point IDCT, the clock cycles required are 64. the total power dissipation, as well as energy consumption centred on information on routing and post placement, are all equal to 4.03 mW and 1.76 mu J for 4-point IDCT/IDST and 3.06 mu J for 8-point IDCT, respectively. Furthermore, the use of 256 instantiated Processing Elements (PEs) at an operating frequency of 200.0 MHz results to a 51.2 Giga Operations Per Second (GOPS) performance and 0.012 GOPS/mW architectural constant for the HARP model on the 28 nm Altera Stratix-V chip. the architecture under the proposal is capable of fully sustaining a format of Full HD 1080P at 30 fps on FPGA.

关键词： IDCT IDST HEVC HARP CGRA Multicore NoC RISC FPGA

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Gemini: A Computation-Centric Distributed Graph Processing system 12

Gemini: A Computation-Centric Distributed Graph Processing S...

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12th USENIX symposium on operating systems design and implementation (osdi)

作者： Zhu, Xiaowei Chen, Wenguang Zheng, Weimin Ma, Xiaosong Tsinghua Univ Dept Comp Sci & Technol TNLIST Beijing Peoples R China Tsinghua Univ Yangtze Delta Reg Inst Technol Innovat Ctr Yinzhou Yinzhou Zhejiang Peoples R China Hamad Bin Khalifa Univ Qatar Comp Res Inst Doha Qatar

ISBN: (纸本)9781931971331

Traditionally distributed graph processing systems have largely focused on scalability through the optimizations of inter-node communication and load balance. However, they often deliver unsatisfactory overall processing efficiency compared with shared-memory graph computing frameworks. We analyze the behavior of several graph-parallel systems and find that the added overhead for achieving scalability becomes a major limiting factor for efficiency, especially with modern multi-core processors and high-speed interconnection networks. Based on our observations, we present Gemini, a distributed graph processing system that applies multiple optimizations targeting computation performance to build scalability on top of efficiency. Gemini adopts (1) a sparse-dense signal-slot abstraction to extend the hybrid push-pull computation model from shared-memory to distributed scenarios, (2) a chunk-based partitioning scheme enabling low-overhead scaling out designs and locality-preserving vertex accesses, (3) a dual representation scheme to compress accesses to vertex indices, (4) NUMA-aware sub-partitioning for efficient intra-node memory accesses, plus (5) locality-aware chunking and fine-grained work-stealing for improving both inter-node and intra-node load balance, respectively. Our evaluation on an 8-node high-performance cluster (using five widely used graph applications and five real-world graphs) shows that Gemini significantly outperforms all well-known existing distributed graph processing systems, delivering up to 39.8 x (from 8.91x) improvement over the fastest among them.

关键词： Scalability

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F4: Facebook's warm blob storage system 11

F4: Facebook's warm blob storage system

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11th USENIX symposium on operating systems design and implementation, osdi 2014

作者： Muralidhar, Subramanian Lloyd, Wyatt Roy, Sabyasachi Hill, Cory Lin, Ernest Liu, Weiwen Pan, Satadru Shankar, Shiva Sivakumar, Viswanath Tang, Linpeng Kumar, Sanjeev Facebook Inc. University of Southern California United States Princeton University United States

ISBN: (纸本)9781931971164

Facebook's corpus of photos, videos, and other Binary Large OBjects (BLOBs) that need to be reliably stored and quickly accessible is massive and continues to grow. As the footprint of BLOBs increases, storing them in our traditional storage system, Haystack, is becoming increasingly inefficient. To increase our storage efficiency, measured in the effective-replication-factor of BLOBs, we examine the underlying access patterns of BLOBs and identify temperature zones that include hot BLOBs that are accessed frequently and warm BLOBs that are accessed far less often. Our overall BLOB storage system is designed to isolate warm BLOBs and enable us to use a specialized warm BLOB storage system, f4. f4 is a new system that lowers the effective-replication-factor of warm BLOBs while remaining fault tolerant and able to support the lower throughput demands. f4 currently stores over 65PBs of logical BLOBs and reduces their effective-replication-factor from 3.6 to either 2.8 or 2.1. f4 provides low latency;is resilient to disk, host, rack, and datacenter failures;and provides sufficient throughput for warm BLOBs. © 2014 by the USENIX Association. All Rights Reserved.

关键词： Social networking (online)

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design, simulation and implementation of a 300W 24V power converters for magnetic levitation vertical axis wind turbine system 4

Design, simulation and implementation of a 300W 24V power co...

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4th International Malaysia-Ireland Joint symposium on Engineering, Science and Business, IMiEJS 2014

作者： Aihsan, M.Z. Baharudin, N.H. Mansur, T.M.N.T. Ali, R.B. Sing, L.S. Rahman, N.A. Electrical System Engineering University Malaysia Perlis Malaysia

ISBN: (纸本)9783038352792

this paper presents a 300W AC/DC/AC power converter for wind energy system. Magnetic Levitation Vertical Axis Wind Turbine is used to harness energy at low wind speed of less than 3 m/s which is suitable for residential area in Malaysia. three phase voltage produces by wind turbine is rectified using three phase rectifier. A boost converter is employed to convert the rectified DC voltage to a higher level. the output stage consists of full bridge circuit that produces asinusoidal AC voltage using SPWM switching technique for common AC loads. When operating inrated condition, this system reduces 300W of energy consumption from utility © (2014) Trans Tech Publications, Switzerland.

关键词： Magnetic levitation

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design of Synchronous Pipeline Digital systems operating in Double-Edge of the Clock

Design of Synchronous Pipeline Digital Systems Operating in ...

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IEEE 4th Latin American symposium on Circuits and systems (LASCAS)

作者： Oliveira, Duarte L. Curtinhas, Tiago Faria, Lester A. Romano, Leonardo Inst Tecnol Aeronaut Div Engn Eletron Sjc SP Brazil

ISBN: (纸本)9781424494859;9781467348973

In contemporaneous digital systems the fetch by performance is critical, many times is accomplished through of the use of the pipeline control. In these systems the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design the synchronous digital system to operate in transitions of both edges of the clock signal (double-edge triggered - DET), once it allows a 50% reduction in the frequency of the clock signal, although showing the same processing rate data. In this paper it is proposed a method that synthesizes synchronous digital systems with pipeline control that operate on both edges of the clock signal, using only flip-flops sensitive to a single edge of the clock signal (single-edge triggered flip-flops-SET-FF) as components of the state memory. the proposed method presents very good potential to reduce the problems associated with the clock, has a high probability of practical implementation with low penalty on area.

关键词： clocks flip-flops logic design

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design of Synchronous Pipeline Digital systems operating in Double-Edge of the Clock

Design of Synchronous Pipeline Digital Systems Operating in ...

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IEEE Latin American symposium on Circuits and systems

作者： Duarte L. Oliveira Tiago Curtinhas Lester A. Faria Leonardo Romano Divis?o de Engenharia Eletr?nica Instituto Tecnológico de Aeronautica - SJC - SP - Brazil Departamento de Engenharia Elétrica Centro Universitario da FEI - SBC - SP - Brazil

ISBN: (纸本)9781467348973

关键词： SET-FF DET Clock

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Foxes and chickens: An android game

Foxes and chickens: An android game

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25th International Conference on Computer Applications in Industry and Engineering, CAINE 2012 and the 4th International symposium on Sensor Network and Application, SNA 2012

作者： Martinez, Justin R. Luo, Wenbin Engineering Department St. Mary's University San Antonio TX 78228 United States

ISBN: (纸本)9781880843888

In this paper, we present the design, implementation, and testing of an Android game, called Foxes and Chickens. It was developed for mobile devices with the Android mobile operating system. the Foxes and Chickens game itself has origins in South America, where it is very popular in some countries. However, to the best of our knowledge, no digital version of the game was available for mass consumption. Our research seeks to remedy this vacancy with the goal of adding values and enjoyment to users of the Android mobile devices. After going through strict software engineering processes of specification, design, coding, and testing, we successfully developed the game, as shown at the following link: http://***/watchv=xeXYiR3Qwio. the game Foxes and Chickens is available for download from the Android market for anyone with an Android powered device. It has been tested for compatibility on the following mobile devices: T-Mobile's G1, HTC MyTouch, and Verizon's Motorola Droid. It should run on other compatible Android handsets as well. Copyright © 2012 by International Society of Computers and their Applications (ISCA).

关键词： Android (operating system)

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design and implementation of a PTP clock infrastructure for the Linux kernel

Design and implementation of a PTP clock infrastructure for ...

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4th IEEE symposium on Precision Clock Synchronization for Measurement Control and Communication, ISPCS 2010

作者： Cochran, Richard Marinescu, Cristian OMICRON Electronics GmbH Oberes Ried 1 6833 Klaus Austria

ISBN: (纸本)9781424459797

Many distributed systems need some sort of synchronization in order to achieve their objectives. the IEEE 1588 Precision Time Protocol (PTP) was designed to achieve synchronization among distributed clocks using a non-deterministic communication medium like Ethernet. Since Linux is becoming a leading operating system in areas like distributed measurement and control or industrial automation, we found it necessary to design and implement a PTP clock infrastructure within the Linux kernel. the paper explains the overall design goals, details the decisions taken, and highlights the resulting software architecture. the case study is based on the results achieved using the new infrastructure. © 2010 IEEE.

关键词： Synchronization

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High-level synthesis of a unified 2-D DWT system architecture for JPEG2000 using FPGAs

High-level synthesis of a unified 2-D DWT system architectur...

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Pacific Rim symposium on Image and Video Technology

作者： Sameen, Ishmael Chang, Yoong Choon Ng, Mow Song Goi, Bok-Min Lee, Chee Siong Faculty of Engineering Multimedia University Cyberjaya Malaysia Faculty of Engineering and Science Universiti Tunku Abdul Rahman Kuala Lumpur Malaysia Penang Design Center Intel Microelectronics Sdn. Bhd. Penang Malaysia

ISBN: (纸本)9780769542850

In this paper, a programmable 2-D DWT system architecture designed for the JPEG2000 standard is proposed. the proposed system architecture, developed through an iterative design space exploration methodology using Altera's C2H compiler, provides a significant 2-D DWT performance improvement when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance for high resolution grayscale images up to 1280 x 720 (720p) when synthesized and benchmarked in an Altera DE3 Stratix III FPGA board. © 2010 IEEE.

关键词： Discrete wavelet transforms

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