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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core architectures 24

Globally Asynchronous Locally Synchronous Simulation of NoCs...

引用

24th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Eggenberger, Marcus Strobel, Manuel Radetzki, Martin Univ Stuttgart Inst Tech Informat Pfaffenwaldring 5b D-70569 Stuttgart Germany

ISBN: (纸本)9781467387767

We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly differ not only in the number of processing elements but also in the on-chip communication architecture, the memory subsystem, and the computational performance of an individual core. Proven multi-core simulation approaches do not consider such architectural aspects and thus suffer limited performance when being applied to many-core architectures. To enable high performance simulation, we identify conceptual drawbacks of state of the art parallel simulation approaches and consequently propose a novel globally asynchronous locally synchronous (GALS) simulation concept suited for many core architectures. Our results show that our GALS simulation approach yields a speedup of up to 2.3 over parallel discrete event simulation.

关键词： cycle accurate many-core network on chip NoC parallel simulation simulation

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Boosting an Embedded Relational Database Management System with Graphics processing Units 5

Boosting an Embedded Relational Database Management System w...

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5th international conference on Data Management Technologies and Applications (DATA)

作者： Cremer, Samuel Bagein, Michel Mahmoudi, Said Manneback, Pierre Univ Mons Dept Comp Sci Rue Houdain 9 B-7000 Mons Belgium

ISBN: (纸本)9789897581939

Concurrently, with the rise of Big Data systems, relational database management systems (RDBMS) are still widely exploited in servers, client devices, and even embedded inside end-user applications. In this paper, it is suggest to improve the performance of SQLite, the most deployed embedded RDBMS. the proposed solution, named CuDB, is an "In-Memory" Database System (IMDB) which attempts to exploit specificities of modern CPU / GPU architectures. In this study massively parallel processing was combined with strategic data placement, closer to computing units. According to content and selectivity of queries, the measurements reveal an acceleration range between 5 to 120 times

关键词： In-memory Database Systems Embedded Databases Relational Database Management Systems GPU

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parallel floating-point expansions for extended-precision GPU computations 27

Parallel floating-point expansions for extended-precision GP...

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27th IEEE international conference on Application-specific Systems, architectures and Processors (ASAP)

作者： Collange, Sylvain Joldes, Mioara Muller, Jean-Michel Popescu, Valentina INRIA Rennes France CNRS LAAS Toulouse France ENS CNRS Lyon France ENS Lyon France

ISBN: (纸本)9781509015030

GPUs are an important hardware development platform for problems where massive parallel computations are needed. Many of these problems require a higher precision than the standard double floating-point (FP) available. One common way of extending the precision is the multiple-component approach, in which real numbers are represented as the unevaluated sum of several standard machine precision FP *** representation is called a FP expansion and it offers the simplicity of using directly available and highly optimized FP operations. In this article we present new data-parallel algorithms for adding and multiplying FP expansions specially designed for extended precision computations on GPUs. these are generalized algorithms that can manipulate FP expansions of different sizes (from double-double up to a few tens of doubles) and ensure a certain worst case error bound on the results.

关键词： floating-point arithmetic floating-point expansions high precision arithmetic multiple-precision arithmetic graphics processing unit parallel computations

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Exploring ilp and tlp on a polymorphic vliw processor 30th

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30th international conference on Architecture of Computing Systems, ARCS 2017

作者： Brandon, Anthony Hoozemans, Joost van Straten, Jeroen Wong, Stephan Computer Engineering Lab Delft University of Technology Delft Netherlands

ISBN: (纸本)9783319549989

In today’s computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are very well-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamically depending on the performance needs of the application. this approach becomes less efficient when the number of cores does not match the number of parallel threads. Furthermore, the heterogeneity of (fixed) cores cannot be increased indefinitely as it would result in even higher degrees of mismatching and increased movement of instruction and data streams. In this paper, we are proposing a polymorphic processor, based on VLIW architectures, that can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermore, we are executing one single generic binary while performing these reconfigurations. In order to show the effectiveness of our approach, we synthesized different versions of the core to represent fixed heterogeneous cores and compared them to the dynamic implementation of the core. Our experiments show that the dynamically adaptive solution performs on average 7% faster and uses 5% less area than a platform which consists of fixed cores with 1.5× as many datapaths. © Springer international Publishing AG 2017.

关键词： parallel processing systems

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Asynchronous parallel nonconvex large-scale optimization

Asynchronous parallel nonconvex large-scale optimization

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IEEE international conference on Acoustics, Speech and Signal processing

作者： L. Cannelli F. Facchinei V. Kungurtsev G. Scutari School of Industrial Engineering Purdue University USA Dept. of Computer Control and Management Engineering University of Rome "La Sapienza" Italy Agent Technology Center Czech Technical University in Prague Czech Republic

ISBN: (纸本)9781509041183

We propose a novel parallel asynchronous algorithmic framework for the minimization of the sum of a smooth (nonconvex) function and a convex (nonsmooth) regularizer. the framework hinges on Successive Convex Approximation (SCA) techniques and on a novel probabilistic model which describes in a unified way a variety of asynchronous settings in a more faithful and exhaustive way with respect to state-of-the-art models. Key features of our framework are: i) it accommodates inconsistent read, meaning that components of the variables may be written by some cores while being simultaneously read by others;ii) it covers in a unified way several existing methods;and iii) it accommodates a variety of parallel computing architectures. Almost sure convergence to stationary solutions is proved for the general case, and iteration complexity analysis is given for a specific version of our model. Numerical results show that our scheme outperforms existing asynchronous ones.

关键词： Asynchronous algorithms big-data inconsistent read nonconvex constrained optimization Asynchronous Constrained optimization Probabilistic Model Frameworks parallel processing (COMPUTERS) parallel Lines Road Convexity core

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Improving Hash Distributed A* for Shared Memory architectures Using Abstraction 16th

Improving Hash Distributed A* for Shared Memory Architecture...

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16th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Sanz, Victoria De Giusti, Armando Naiouf, Marcelo Natl Univ La Plata Sch Comp Sci III LIDI La Plata Argentina Minist Sci Technol & Product Innovat CONICET Buenos Aires DF Argentina

ISBN: (纸本)9783319495835;9783319495828

the A* algorithm is generally used to solve combinatorial optimization problems, but it requires high computing power and a large amount of memory, hence, efficient parallel A* algorithms are needed. In this sense, Hash Distributed A* (HDA*) parallelizes A* by applying a decentralized strategy and a hash-based node distribution scheme. However, this distribution scheme results in frequent node transfers among processors. In this paper, we present Optimized AHDA*, a version of HDA* for shared memory architectures, that uses an abstraction-based node distribution scheme and a technique to group several nodes before transferring them to the corresponding thread. Both methods reduce the amount of node transfers and mitigate communication and contention. We assess the effect of each technique on algorithm performance. Finally, we evaluate the scalability of the proposed algorithm, when it is run on a multicore machine, using the 15-puzzle as a case study.

关键词： HDA* for shared memory architectures Abstraction-based node distribution scheme Hash-based node distribution scheme Scalability Combinatorial optimization problems

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parallel Integer Polynomial Multiplication 18

Parallel Integer Polynomial Multiplication

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18th international Symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： Chen, Changbo Covanov, Svyatoslav Mansouri, Farnam Maza, Marc Moreno Xie, Ning Xie, Yuzhen Univ Western Ontario Dept Comp Sci London ON N6A 5B7 Canada

We propose a new algorithm for multiplying dense polynomials with integer coefficients in a parallel fashion, targeting multi-core processor architectures. Complexity estimates and experimental comparisons demonstrate... 详细信息

ISBN: (纸本)9781509057078

关键词： Polynomial algebra symbolic computation parallel processing cache complexity multi-core architectures

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Porting of parallel applications to reconfigurable computer systems with various architectures and configurations 5

Porting of parallel applications to reconfigurable computer ...

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5th international conference on Informatics, Electronics and Vision (ICIEV)

作者： Dordopulo, Alexey Igorevich Kovalenko, Vasiliy Borisovich Gudkov, Viacheslav Alexandrovich Slasten, Liubov Mikhailovna Southern Fed Univ Kalyaev Sci Res Inst Multiprocessor Comp Syst Taganrog Russia

ISBN: (纸本)9781509012695

A problem of porting of parallel applications from one reconfigurable computer system to another is considered in the paper. the reconfigurable computer systems can have different soft-architectures and different configurations, which are used for implementation of the application. A new method of porting of parallel applications, which allows estimation of possibility of porting from an initial soft-architecture to a target soft architecture, is suggested in the paper. Owing to the use of the new porting method, the application is ported to another soft architecture without modification of its initial code, and its information graph is automatically mapped on various soft architectures.

关键词： porting soft-architecture reconfigurable computer system parallel application macoobject high-level programming language COLAMO soft-architecture description language SADL

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A cost effective dual band chebyshev parallel coupled microstrip line bandpass filter for ISM band applications

A cost effective dual band chebyshev parallel coupled micros...

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international conference on Wireless Communications, Signal processing and Networking (WiSPNET)

作者： M. Bhagavathi Priya K. Ramprakash P. Pavithra D. Allin Joe Department of Electronics and Communication Engineering Kumaraguru College of Technology Coimbatore India

ISBN: (纸本)9781509044436;9781509044429

In this paper, a 5th order dual band chebyshev parallel coupled microstrip line bandpass filter is designed for Industrial, Scientific, and Medical (ISM) radio band and so this filter allows 2.4 GHz and 5 GHz frequency bands. ISM band is used in dual band routers and 2.4/5 GHz transverter. the designed filter is simulated using Advanced Design System (ADS) simulator and implemented on FR4 substrate with relative dielectric constant of 4.6. the simulated design has high return loss and low insertion loss on the desired ISM frequency bands.

关键词： Microstrip Substrates Dual band Insertion loss conferences Band-pass filters Microstrip filters

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Shared Memory Tile-Based vs Hybrid Memory GOP-Based parallel algorithms for HEVC Encoder 16th

Shared Memory Tile-Based vs Hybrid Memory GOP-Based Parallel...

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16th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Migallon, Hector Lopez-Granado, Otoniel Galiano, Vicente Pinol, Pablo Malumbres, Manuel P. Miguel Hernandez Univ Dept Phys & Comp Architecture Avda Univ S-N Alicante 03202 Spain

ISBN: (纸本)9783319495835;9783319495828

After the emergence of the new High Efficiency Video Coding standard, several strategies have been followed in order to take advantage of the parallel features available in it. Many of the parallelization approaches in the literature have been performed in the decoder side, aiming at achieving real-time decoding. However, the most complex part of the HEVC codec is the encoding side. In this paper, we perform a comparative analysis of two parallelization proposals. One of them is based on tiles, employing shared memory architectures and the other one is based on Groups Of Pictures, employing distributed shared memory architectures. the results show that good speed-ups are obtained for the tile-based proposal, especially for high resolution video sequences, but the scalability decreases for low resolution video sequences. the GOP-based proposal outperforms the tile-based proposal when the number of processes increases. this benefit grows up when low resolution video sequences are compressed.

关键词： HEVC Video coding parallel encoding Shared memory Distributed shared memory

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