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Ultrasound Reflector Recognition and Tracking Technique for Two-Phase Flow 24

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24th international conference on Nuclear Engineering

作者： Povolny, Antonin Kikura, Hiroshige Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9780791850053

Two-phase liquid-gas flow occurs in many safety systems of nuclear reactors as well as in reactor cores. To further improve both safety and commercial performance of nuclear reactors, it is important to improve numerical codes and deepen the understanding of two-phase flow with experiments on gas behaviour in liquids. Among several available measurement methods, ultrasound based methods are affordable and easy to use even for high pressure/temperature flows in non-transparent pipes. Ultrasound Reflector Recognition and Tracking Technique (URRTT) has been developed as a new technique. It uses an ultrasound transducer, which emits ultrasound beam into the liquid with gas bubbles. the phase interface reflects the beam and because of that, the phase interface can be recognised in the reflected signal and the distance (from the transducer) can be calculated. the core of this technique is the tracking algorithm that can separate data of different bubbles from each other and obtain their one dimensional trajectories along the measurement line. Trajectories measured simultaneously by more transducers (at different positions or from different directions) can be combined. that means trajectory of the bubble interface from one transducer can be connected to trajectory from a different transducer and by doing so, a secondary data can be obtained using the information that those trajectories belong to the same bubble. As an example, the average two dimensional velocity between two parallel measurement lines can be obtained. Another example is the measurement of the bubble size using one measurement line with two oppositely oriented transducers. Experiments have been conducted to prove the concept of URRTT. Results have been validated to data obtained by the image processing of footage taken by a high speed camera. the results obtained by URRTT can be of high value since each detected bubble is measured individually and thus, difference in the bubble behaviour based on the size,

关键词： Trajectories (Physics) High pressure (Physics) Flow (Dynamics) algorithms Temperature Transparency Ultrasonic transducers Pipes Signals Safety Two-phase flow Ultrasound Transducers Phase interfaces Bubbles Image processing Nuclear reactors

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Improving Performance of DAOPHOT-FIND by Using GPU Architecture 6th

Improving Performance of DAOPHOT-FIND by Using GPU Architect...

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6th international conference on Supercomputing in Mexico (ISUM)

作者： Hernandez Perez, Ruben Gabbasov, Ruslan Suarez Cansino, Joel Univ Autonoma Estado Hidalgo Inst Ciencias Basicas & Ingn Ctr Invest Tecnol Informac & Sistemas Carretera Pachuca Tulancingo Km 4-5 Mineral De La Reforma 42090 Hgo Mexico

ISBN: (纸本)9783319322438;9783319322421

In astronomy there have been big changes in the availability of data, much of it provided freely and publicly via internet, allowing people to access the same data as used by professional astronomers for their own investigations. the data obtained from different telescopes have increased in size too, forcing the community to boost the performance of algorithms for image processing, pattern recognition, and, in particular, tasks for finding and characterizing astronomical objects. One of such packages is DAOPHOT designed to deal with crowded astronomical fields. However, the tasks are computationally intensive because they require the execution of many floating point operations. In order to face such computational challenge, we propose an implementation of DAOPHOT's particular task FIND, using massive parallel computation architecture supported by GPUs, which allows us to process large images at least two times faster. this work presents the analysis and comparison of time complexity between the implementations of the FIND algorithm both in CPU and GPU.

关键词： Graphics processing unit

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Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms

Optimizing interconnection complexity for realizing fixed pe...

引用

international conference on Field Programmable Logic and Applications

作者： Ren Chen Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California Los Angeles USA

In hardware implementation of several widely used data and signal processing algorithms, data permutations need to be performed between the consecutive computation stages consisting of parallel computational units. Recently, some highly data parallel streaming architectures for data permutation have been proposed to achieve high throughput. However, the interconnection complexity of these designs increases dramatically with the problem size and data parallelism. In this paper, we develop a hardware structure to perform data permutation with optimized interconnection complexity, denned as the interconnection area per throughput. We propose a novel design technique such that the required interconnection logic is highly reduced for realizing a fixed permutation on streaming data. Our experimental results show that the proposed design technique reduces interconnection complexity by 27.3% to 75.8%, and improves the throughput by 5.3%~129% and the energy efficiency by 1.2×~3.5× compared with the state-of-the-art.

关键词： Multiplexing

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Towards an Automatic Prediction of Image processing algorithms Performances on Embedded Heterogeneous architectures 44

Towards an Automatic Prediction of Image Processing Algorith...

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44th Annual international conference on parallel processing Workshops (ICPPW)

作者： Saussard, Romain Bouzid, Boubker Vasiliu, Marius Reynaud, Roger Renault SAS Guyancourt France Univ Paris 11 Inst Elect Fondamentale Orsay France

ISBN: (纸本)9781467375894

Image processing algorithms are widely used in the automotive field for ADAS (Advanced Driver Assistance System) purposes. To embed these algorithms, semiconductor companies offer heterogeneous architectures which are composed of different processing units, often with massively parallel computing unit. However, embedding complex algorithms on these SoCs (System on Chip) remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on processing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processing algorithms on different computing units of a given heterogeneous SoC. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms to embed, and a few characteristics of computing units.

关键词： Heterogeneous architectures Performance Prediction Image processing

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Study on the English Corresponding Unit of Chinese Clause

Study on the English Corresponding Unit of Chinese Clause

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5th international conference on Natural Language processing and Chinese Computing (NLPCC) / 24th international conference on Computer processing of Oriental Languages (ICCPOL)

作者： Feng, Wenhe Yang, Yi Li, Yancui Li, Xia Ren, Han Wuhan Univ Wuhan 430073 Hubei Peoples R China Guangdong Univ Foreign Studies Guangzhou 510006 Guangdong Peoples R China Ural Fed Univ Ekaterinburg 620000 Russia Henan Inst Sci & Technol Xinxiang 453003 Henan Peoples R China

ISBN: (纸本)9783319504964;9783319504957

this paper annotates the English corresponding units of Chinese clauses in Chinese-English translation and statistically analyzes them. Firstly, based on Chinese clause segmentation, we segment English target text into corresponding units (clause) to get a Chinese-to-English clause-aligned parallel corpus. then, we annotate the grammatical properties of the English corresponding clauses in the corpus. Finally, we find the distribution characteristics of grammatical properties of English corresponding clauses by statistically analyzing the annotated corpus: there are more clauses (1631,74.41%) than sentences (561,25.59%);there are more major clauses (1719,78.42%) than subordinate clauses (473,21.58%);there are more adverbial clauses (392,82.88%) than attributive clauses (81,17.12%) and more non-defining clauses (358,75.69%) than restrictive relative clauses (115,24.31%) in subordinate clauses;and there are more simple clauses (1142,52.1%) than coordinate clauses (1050,47.9%).

关键词： Clauses parallel corpus Clause-based Clause alignment Discourse-based translation Chinese-to-English translation

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ALMOS Many-Core Operating System Extension with New Secure-Enable Mechanisms for Dynamic Creation of Secure Zones

ALMOS Many-Core Operating System Extension with New Secure-E...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Maria Méndez Real Vincent Migliore Vianney Lapotre Guy Gogniat UMR 6285 Lab-STICC Lorient France

Many-core architectures are becoming a major execution platform in order to face the increasing number of applications to be executed in parallel. Such an approach is very attractive in order to offer users with high performance. However it introduces some key challenges in terms of security as some malicious applications may compromise the whole system. A defense-in-depth approach relying on hardware and software mechanisms is thus mandatory to increase the level of protection. this work focuses on the Operating System (OS) level and proposes a set of operating system services able to dynamically create physical isolated secure zones for sensitive applications in many-core platforms. these services are integrated into the ALMOS OS deployed in the TSAR many-core architecture, and evaluated in terms of security level and induced performance overhead.

关键词： Security Monitoring Resource management Multicore processing Clustering algorithms Virtual machining

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Novel Heuristic Mapping algorithms for Design Space Exploration of Multiprocessor Embedded architectures

Novel Heuristic Mapping Algorithms for Design Space Explorat...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Sima Sinaei Omid Fatemi Electrical and Computer Engineering Department University of Tehran Tehran Iran

Electronic System level design has an important role in the multi-processor embedded system on chip design. Two important steps in this process are evaluation of a single design configuration and design space exploration. In the first part of design process, high-level simple analytical models for application mapping and evaluation are used and modified aiming at accelerating the evaluation of a single design configuration. Using the analytical model the design space is pruned and explored at high speed with low accuracy. In the second part of the design process, two Multi Objective Optimization algorithms based on Particle Swarm Optimization and Simulated Annealing have been proposed to perform design space exploration of the pruned design space with higher accuracy taking advantages of low-level architectural simulation engines. the results obtained by proposed algorithms will provide the designer more accurate solutions within an acceptable time. Considering the MJPEG application as the case study, each of these methods produces a set of near-optimal points. Simulation results show that the proposed methods can lead to near-optimal design configurations with acceptable accuracy in reasonable time.

关键词： Energy consumption Mathematical model Space exploration Memory management Algorithm design and analysis Analytical models Optimization

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Predicting Performance and Power Consumption of parallel Applications

Predicting Performance and Power Consumption of Parallel App...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Daniele De Sensi Dept. of Computer Science Univ. of Pisa

Current architectures provide many control knobs for the reduction of power consumption of applications, like reducing the number of used cores or scaling down their frequency. However, choosing the right values for these knobs in order to satisfy requirements on performance and/or power consumption is a complex task and trying all the possible combinations of these values is an unfeasible solution since it would require too much time. For this reasons, there is the need for techniques that allow an accurate estimation of the performance and power consumption of an application when a specific configuration of the control knobs values is used. Usually, this is done by executing the application with different configurations and by using these information to predict its behaviour when the values of the knobs are changed. However, since this is a time consuming process, we would like to execute the application in the fewest number of configurations possible. In this work, we consider as control knobs the number of cores used by the application and the frequency of these cores. We show that on most Parsec benchmark programs, by executing the application in 1% of the total possible configurations and by applying a multiple linear regression model we are able to achieve an average accuracy of 96% in predicting its execution time and power consumption in all the other possible knobs combinations.

关键词： Power demand Prediction algorithms Time-frequency analysis Predictive models Linear regression Heuristic algorithms Runtime

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Efficient convolution architectures for convolutional neural network

Efficient convolution architectures for convolutional neural...

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international conference on Wireless Communications and Signal processing (WCSP)

作者： Jichen Wang Jun Lin Zhongfeng Wang School of Electronic Science and Engineering Nanjing University P.R. China

ISBN: (纸本)9781509028610

Convolutional Neural Network (CNN) is the state-of-the-art deep learning approach employed in various applications due to its remarkable performance. Convolutions in CNNs generally dominate the overall computation complexity and thus consume major computational power in real implementations. In this paper, efficient hardware architectures incorporating parallel fast finite impulse response (FIR) algorithm (FFA) for CNN convolution implementations are discussed. the theoretical derivation of 3 and 5 parallel FFAs is presented and the corresponding 3 and 5 parallel fast convolution units (FCUs) are proposed for most commonly used 3 × 3 and 5 × 5 convolutional kernels in CNNs, respectively. Compared to conventional CNN convolution architectures, the proposed FCUs reduce the number of multiplications used in convolutions significantly. Additionally, the FCUs minimize the number of reads from the feature map memory. Furthermore, a reconfigurable FCU architecture which suits the convolutions of both 3 × 3 and 5 × 5 kernels is proposed. Based on this, an efficient top-level architecture for processing a complete convolutional layer in a CNN is developed. To quantize the benefits of the proposed FCUs, the design of an FCU is coded with RTL and synthesized with TSMC 90nm CMOS technology. the implementation results demonstrate that 30% and 36% of the computational energy can be saved compared to conventional solutions with 3 × 3 and 5 × 5 kernels in CNN, respectively.

关键词： Convolution Kernel Computer architecture Finite impulse response filters Hardware Two dimensional displays Convolutional codes

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Optimized GPU implementation for dynamic programming in image data processing

Optimized GPU implementation for dynamic programming in imag...

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IEEE international conference on Performance, Computing and Communications (IPCCC)

作者： Jing Ke Tomasz Bednarz Arcot Sowmya DATA 61 CSIRO University of New South Wales Sydney Australia DATA 61 CSIRO Sydney Australia School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781509052530

It is a trend now that computing power through parallelism is provided by multi-core systems or heterogeneous architectures for High Performance Computing (HPC) and scientific computing. Although many algorithms have been proposed and implemented using sequential computing, alternative parallel solutions provide more suitable and high performance solutions to the same problems. In this paper, three parallelization strategies are proposed and implemented for a dynamic programming based cloud smoothing application, using both shared memory and non-shared memory approaches. the experiments are performed on NVIDIA GeForce GT750m and Tesla K20m, two GPU accelerators of Kepler architecture. Detailed performance analysis is presented on partition granularity at block and thread levels, memory access efficiency and computational complexity. the evaluations described show high approximation of results with high efficiency in the parallel implementations, and these strategies can be adopted in similar data analysis and processing applications.

关键词： Instruction sets Dynamic programming Heuristic algorithms Smoothing methods Graphics processing units Memory management

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