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Leverage cache replacement policy in multicore processors

Leverage cache replacement policy in multicore processors

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IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Marius Geanta Lavinia Ghica Nicolae Tapus Bucharest Romania “Politehnica” University of Bucharest Bucharest Romania Computer Science Departament “Politehnica” University of Bucharest Bucharest Romania

ISBN: (纸本)9781509039005

Computer hardware is currently moving towards heavily parallelized architectures with multiprocessors, multicore and chip multithreaded designs. Cache memory, the fastest component of the memory hierarchy, adapts to this new kind of parallel systems in order to provide the promised performance increase. Current cache designs have limitations that can be transformed into optimization opportunities both in hardware and software. this paper provides a detailed research of cache performance in multicore processors, considering critical hardware aspects. A new solution is proposed to improve the current performance: an optimized replacement policy for the shared cache level. From experiments run on four and eight core setups in a multicore simulator, the proposed enhancements achieve up to 30% execution speed increase over the default setup.

关键词： Multicore processing Program processors Hardware throughput Approximation algorithms Electronics packaging

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A Mobile SoC-Based Platform for Evaluating Hearing Aid algorithms and architectures 5

A Mobile SoC-Based Platform for Evaluating Hearing Aid Algor...

引用

5th IEEE international conference on Consumer Electronics Berlin

作者： Seifert, Christopher Paya-Vaya, Guillermo Blume, Holger Herzke, Tobias Hohmann, Volker Leibniz Univ Hannover & Cluster Excellence Hearin Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany Hortech gGmbH D-26129 Oldenburg Germany Carl von Ossietzky Univ Oldenburg & Cluster Excel Med Phys D-26129 Oldenburg Germany

ISBN: (纸本)9781479987481

Current research on audio signal processing algorithms for digital hearing aid devices is extremely pushing the performance demands. Nowadays, there is a trend of using several microphones in such systems (e.g., binaural systems) to improve the speech perception of a hearing impaired person. However, there is a lack of mobile platforms, capable of processing such algorithms in real-time. this paper presents a new mobile SoC-based evaluation and development platform (including a multichannel audio extension board), specially thought not only for evaluating new hearing aid signal processing algorithms but also to develop new hardware co-processor architectures, that could be integrated in current hearing aid devices to improve their performance with a minimal extra energy consumption.

关键词： Hearing aids

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Using HPX and OP2 for Improving parallel Scaling Performance of Unstructured Grid Applications

Using HPX and OP2 for Improving Parallel Scaling Performance...

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international conference on parallel processing Workshops (ICPPW)

作者： Zahra Khatami Hartmut Kaiser J. Ramanujam The STE∥AR Group Baton Rouge Louisiana USA Center for Computation and Technology Louisiana State University

ISBN: (纸本)9781509028269

Computer scientists and programmers face the difficultly of improving the scalability of their applications while using conventional programming techniques only. As a base-line hypothesis of this paper we assume that an advanced runtime system can be used to take full advantage of the available parallel resources of a machine in order to achieve the highest parallelism possible. In this paper we present the capabilities of HPX - a distributed runtime system for parallel applications of any scale - to achieve the best possible scalability through asynchronous task execution [1]. OP2 is an active library which provides a framework for the parallel execution for unstructured grid applications on different multi-core/many-core hardware architectures [2]. OP2 generates code which uses OpenMP for loop parallelization within an application code for both single-threaded and multi-threaded machines. In this work we modify the OP2 code generator to target HPX instead of OpenMP, i.e. port the parallel simulation backend of OP2 to utilize HPX. We compare the performance results of the different parallelization methods using HPX and OpenMP for loop parallelization within the Airfoil application. the results of strong scaling and weak scaling tests for the Airfoil application on one node with up to 32 threads are presented. Using HPX for parallelization of OP2 gives an improvement in performance by 5%-21%. By modifying the OP2 code generator to use HPX's parallel algorithms, we observe scaling improvements by about 5% as compared to OpenMP. To fully exploit the potential of HPX, we adapted the OP2 API to expose a future and dataflow based programming model and applied this technique for parallelizing the same Airfoil application. We show that the dataflow oriented programming model, which automatically creates an execution tree representing the algorithmic data dependencies of our application, improves the overall scaling results by about 21% compared to OpenMP. Our results show

关键词： Automotive components parallel processing Scalability Programming Instruction sets Runtime Hardware

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Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning

Bridging the FPGA programmability-portability Gap via automa...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Konstantinos Krommydas Ruchira Sasanka Wu-chun Feng Dept. of Computer Science Virginia Tech Intel Corporation

ISBN: (纸本)9781509015047

Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.

关键词： Kernel Field programmable gate arrays Optimization parallel processing Programming Visualization Shift registers

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Unified weighted label propagation algorithm using connection factor 12th

Unified weighted label propagation algorithm using connectio...

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12th international conference on Advanced Data Mining and Applications, ADMA 2016

作者： Wang, Xin Jian, Songlei Lu, Kai Wang, Xiaoping College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9783319495859

With the social networks getting increasingly larger, fast community detection algorithms like the label propagation algorithm, are attracting more attention. But the label propagation algorithm deals vertices with no proper weight, which leads to the loss in the performance. We propose the connection factor of the vertex to measure its influence on the local connectivity. the connection factor can reveal the topological structure feature, and we propose a unified weight to modify the original label propagation algorithm. Experiments show that our Unified Weighted LPA has an average performance promotion from 5% to 10 %, in the best case more than 30%. © Springer international Publishing AG 2016.

关键词： Population dynamics

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Optimal Performance Prediction of ADAS algorithms on Embedded parallel architectures 17

Optimal Performance Prediction of ADAS Algorithms on Embedde...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Saussard, Romain Bouzid, Boubker Vasiliu, Marius Reynaud, Roger Renault SAS Guyancourt France Univ Paris 11 Inst Elect Fondamentale Orsay France

ISBN: (纸本)9781479989379

ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit. Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial. In fact it is not a simple task for automotive industry actors to choose the most suited heterogeneous SoC for a given application. Moreover, embedding complex algorithms on these systems remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on the different computing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processing algorithms applicable on different types of computing units. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms, and a few characteristics of computing units.

关键词： Heterogeneous architectures Embedded Systems Performance Prediction Image processing

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In-Place Data Sliding algorithms for Many-Core architectures 44

In-Place Data Sliding Algorithms for Many-Core Architectures

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44th Annual international conference on parallel processing Workshops (ICPPW)

作者： Gomez-Luna, Juan Chang, Li-Wen Hwu, Wen-Mei W. Sung, I-Jui Guil, Nicolas Univ Cordoba Comp Architecture & Elect Cordoba Spain Univ Illinois Elect & Comp Engn Urbana IL 61801 USA MulticoreWare Inc Champaign IL USA Univ Malaga Comp Architecture Malaga Spain

ISBN: (纸本)9781467375887

In-place data manipulation is very desirable in many-core architectures with limited on-board memory. this paper deals with the in-place implementation of a class of primitives that perform data movements in one direction. We call these primitives Data Sliding (DS) algorithms. Notable among them are relational algebra primitives (such as select and unique), padding to insert empty elements in a data structure, and stream compaction to reduce memory requirements. their in-place implementation in a bulk synchronous parallel model, such as GPUs, is specially challenging due to the difficulties in synchronizing threads executing on different compute units. Using a novel adjacent work-group synchronization technique, we propose two algorithmic schemes for regular and irregular DS algorithms. With a set of 5 benchmarks, we validate our approaches and compare them to the state-of-the-art implementations of these benchmarks. Our regular DS algorithms demonstrate up to 9.11x and 73.25x on NVIDIA and AMD GPUs, respectively, the throughput of their competitors. Our irregular DS algorithms outperform NVIDIA thrust library by up to 3.24x on the three most recent generations of NVIDIA GPUs.

关键词： in-place stream compaction relational algebra

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algorithms and architectures for parallel processing - 14th international conference, ICA3PP 2014, Proceedings

Algorithms and Architectures for Parallel Processing - 14th ...

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14th international conference on algorithms and architectures for parallel processing, ICA3PP 2014

ISBN: (纸本)9783319111933

the proceedings contain 125 papers. the topics discussed include: efficient detection of cloned attacks for large-scale RFID systems;probability based algorithms for guaranteeing the stability of rechargeable wireless sensor networks;PTAs for minimum k-path connected vertex cover in growth-bounded graphs;a simple and effective long duration contact-based utility metric for mobile opportunistic networking;virtual network mapping algorithm in wireless data center networks;a weighted centroid based tracking system in wireless sensor networks;utilizing multiple Xeon phi coprocessors on one compute node;service scheduling algorithm in vehicle embedded middleware;similar samples cleaning in speculative multithreading;equi-join for multiple datasets based on time cost evaluation model;and identifying file similarity in large data sets by modulo file length.

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Task Allocation for Distributed Stream processing

Task Allocation for Distributed Stream Processing

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Annual IEEE international conference on Computer Communications

作者： Raphael Eidenbenz thomas Locher ABB Corporate Research

ISBN: (纸本)9781467399548

there is a growing demand for live, on-the-fly processing of increasingly large amounts of data. In order to ensure the timely and reliable processing of streaming data, a variety of distributed stream processing architectures and platforms have been developed, which handle the fundamental tasks of (dynamically) assigning processing tasks to the currently available physical resources and routing streaming data between these resources. However, while there are plenty of platforms offering such functionality, the theory behind it is not well understood. In particular, it is unclear how to best allocate the processing tasks to the given resources. In this paper, we establish a theoretical foundation by formally defining a task allocation problem for distributed stream processing, which we prove to be NP-hard. Furthermore, we propose an approximation algorithm for the class of series-parallel decomposable graphs, which captures a broad range of common stream processing applications. the algorithm achieves a constant-factor approximation under the assumptions that the number of resources scales at least logarithmically with the number of computational tasks and the computational cost of the tasks dominates the cost of communication.

关键词： Resource management Approximation algorithms Complexity theory Topology Distributed databases Routing Computational efficiency

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algorithms and architectures for parallel processing - 14th international conference, ICA3PP 2014, Proceedings

Algorithms and Architectures for Parallel Processing - 14th ...

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14th international conference on algorithms and architectures for parallel processing, ICA3PP 2014

ISBN: (纸本)9783319111964

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