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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

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FPGA-based accelerator design from a domain-specific language

FPGA-based accelerator design from a domain-specific languag...

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international conference on Field Programmable Logic and Applications

作者： M. Akif Özkan Oliver Reiche Frank Hannig Jürgen Teich Friedrich-Alexander University of Erlangen-Ntirnberg (FAU) Germany

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： Kernel Hardware Computer architecture Programming Field programmable gate arrays Image processing

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X-Ray Computed Tomography Applied to Objects of Cultural Heritage: Porting and Testing the Filtered Back-Projection Reconstruction Algorithm on Low Power Systems-on-Chip

X-Ray Computed Tomography Applied to Objects of Cultural Her...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Elena Corni Lucia Morganti Maria Pia Morigi Rosa Brancaccio Matteo Bettuzzi Giuseppe Levi Eva Peccenini Daniele Cesini Andrea Ferraro Department of Physics and Astronomy University of Bologna Bologna Italy Bologna Section Italian Institute for Nuclear Physics (INFN) Bologna Italy Enrico Fermi Center for Study and Research Roma Italy CNAF Section Italian Institute for Nuclear Physics (INFN) Bologna Italy

the embedded and high-performance computing (HPC) sectors, that in the past were completely separated, are now somehow converging under the pressure of two driving forces: the release of less power consuming server processors and the increased performance of the new low power Systems-on-Chip (SoCs) developed to meet the requirements of the demanding mobile market. this convergence allows the porting to low power embedded architectures of applications that were originally confined to traditional HPC systems. In this paper, we present our experience of porting the Filtered Back-projection Algorithm to a low power, low cost system-on-chip, the NVIDIA Tegra K1, which is based on a quad core ARM CPU and on a NVIDIA Kepler GPU. this Filtered Back-projection Algorithm is heavily used in 3D Tomography reconstruction software. the porting has been done exploiting various programming languages (i.e. OpenMP, CUDA) and multiple versions of the application have been developed to exploit both the SoC CPU and GPU. the performances have been measured in terms of 2D slices (of a 3D volume) reconstructed per time unit and per energy unit. the results obtained with all the developed versions are reported and compared with those obtained on a typical x86 HPC node accelerated with a recent NVIDIA GPU. the best performances are achieved combining the OpenMP version and the CUDA version of the algorithm. In particular, we discovered that only three Jetson TK1 boards, equipped with Giga Ethernet interconnections, allow to reconstruct as many images per time unit as a traditional server, using one order of magnitude less energy. the results of this work can be applied for instance to the construction of an energy-efficient computing system of a portable tomographic apparatus.

关键词： Graphics processing units Image reconstruction Computer architecture Filtering algorithms Computed tomography Radiography

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CUDA Grid-Level Task Progression algorithms 17

CUDA Grid-Level Task Progression Algorithms

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Kartsaklis, Christos Joubert, Wayne Hernandez, Oscar R. Eisenbach, Markus Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781479989379

Tasking is a prominent parallel programming model. In this paper we conduct a first study into the feasibility of task-parallel execution at the CUDA grid, rather than the stream/kernel level, for regular, fixed in-out dependency task graphs, similar to those found in wavefront computational patterns, making the findings broadly applicable. We propose and evaluate three CUDA task progression algorithms, where threadblocks cooperatively process the task graph, and argue about their performance in terms of tasking throughput, atomics and memory IO overheads. Our initial results demonstrate a throughput of 38 million tasks/second on a Kepler K20X architecture.

关键词： parallel architectures parallel programming CUDA grid-level task progression algorithm CUDA task progression algorithm Kepler K20X architecture parallel programming model wavefront computational pattern Computational modeling Graphics processing units Instruction sets Kernel parallel processing Radiation detectors Runtime

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Communication Avoiding algorithms: Analysis and Code Generation for parallel Systems 24

Communication Avoiding Algorithms: Analysis and Code Generat...

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24th international conference on parallel Architecture and Compilation (PACT)

作者： Murthy, Karthik Mellor-Crummey, John Rice Univ Dept Comp Sci Houston TX USA

ISBN: (纸本)9781467395243

Data movement is a critical bottleneck for future generations of parallel systems. the class of .5D communication-avoiding algorithms were developed to address this bottleneck. these algorithms reduce communication and provide strong scaling in both time and energy. As a first step towards automating the development of communication-avoiding libraries, we developed the Maunam compiler. Maunam generates efficient parallel code from a high-level, global view sketch of .5D algorithms that are expressed using symbolic data sizes and numbers of processors. It supports the expression of data movement and communication through high-level global operations such as TILT and CSHIFT as well as through element-wise copy operations. With the latter, wraparound communication patterns can also be achieved using subscripts based on modulo operations. Maunam employs polyhedral analysis to reason about communication and computation present in a .5D algorithm. After partitioning data and computation, it inserts point-to-point and collective communication as needed. Maunam also analyzes data dependence patterns and data layouts to identify reductions over processor subsets. Maunam-generated Fortran+MPI code for 2.5D matrix multiplication running on 4096 cores of a Cray XC30 supercomputer achieves 59 TFlops/s (76% of the machine peak). Our generated parallel code achieves 91% of the performance of a hand-coded version.

关键词： Compilers polyhedral methods reductions modulo operations optimization parallel code generation

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A parallel LUMA-CHROMA FILTERING ARCHITECTURE FOR H.264/AVC DEBLOCKING FILTER 5

A PARALLEL LUMA-CHROMA FILTERING ARCHITECTURE FOR H.264/AVC ...

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5th IEEE international conference on Consumer Electronics Berlin

作者： Kefalas, Nikolaos theodoridis, George Univ Patras ECE Dept VLSI Design Lab Patras 26500 Greece

ISBN: (纸本)9781479987481

A novel architecture for the H.264/AVC deblocking filter is proposed. It includes three filtering units to filter in parallel the luma and chroma components. Also, a proper two dimensional filtering order for the luma edges and a one-dimensional filtering order for the chroma edges are presented. the architecture achieves 750 MHz in 560 MHz in 90nm and 130 nm, respectively, and requires 76 cycles to filter each MB. Compared to existing architectures, it outperforms them in frequency and throughput, while it is the only one that achieves over 60 Fps in 8K-UHD resolution.

关键词： H.264 Deblocking UHD Pipeline throughput

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Research of parallel programming techniques for the hierarchical model based on clusters of SMPs 5th

Research of parallel programming techniques for the hierarch...

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5th international conference on Environmental Science and Information Application Technology (ESIAT)

作者： Zhu, Yong-zhi Yu, Ji-guo Cao, Bao-xiang Qufu Normal Univ Sch Informat Sci & Engn Rizhao Peoples R China

ISBN: (纸本)9781315684895;9781138028142

With the current prevalence of multi-core processors in SMP cluster architectures, mixed-mode programming, using both MPI and OpenMP in the same application, is becoming increasingly important. In this paper we discuss three methods for the parallelization of such algorithms, namely pure MPI parallelization, fine-grain hybrid MPI/OpenMP parallelization, and coarse-grain MPI/OpenMP parallelization. We propose a new hybrid parallel programming method based on architecture hierarchy on SMP cluster. We designed a hierarchical parallel algorithm on the N-body problem, and compare its performance with the traditional hybrid parallel algorithm on the Dawning 5000A cluster. the results indicate that the hierarchical hybrid parallel algorithm has better scalability and speed.

关键词： parallel programming

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Efficient implementation of a fast viewshed algorithm on SIMD architectures 23

Efficient implementation of a fast viewshed algorithm on SIM...

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23rd Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Bravo, Jesus Carabano Sarjakoski, Tapani Westerholm, Jan Abo Akad Univ Dept IT Joukahainengatan 3-5 FIN-20520 Turku Finland Finnish Geodet Inst Dept Geoinformat & Cartog Masala 02431 Finland

ISBN: (纸本)9781479984909

Viewshed refers to the land area that is visible to an observer placed in a point of a terrain. Due to the advances in remote sensing technologies the volume of data is today beyond the capability of traditional GIS tools and therefore new and fast algorithms become essential. In this paper we present an efficient implementation of the XDRAW algorithm [5] to quickly compute viewsheds on very large digital elevation models. We redesign the algorithm to make it IO-efficient and compatible with modern STAID architectures. Our implementation is able to compute viewsheds on digital elevation models at the rate of 10' points per second on an Intel quad-core CPU with AVX2 technology, which makes the algorithm suitable for real-time applications.

关键词： viewshed gis simd parallel real-time

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parallel Strategies for Harmony Search on CUDA to Solve Traveling Salesman Problem 5

Parallel Strategies for Harmony Search on CUDA to Solve Trav...

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5th international conference on IT Convergence and Security (ICITCS)

作者： Le, Kang Chian Abdullah, Rosni Univ Sains Malaysia Sch Comp Sci Usm 11800 Penang Malaysia Univ Sains Malaysia Sch Comp Sci Natl Adv Ctr Nav6 IPv6 Usm 11800 Penang Malaysia

ISBN: (纸本)9781467365376

this paper presents parallel strategies applied to Harmony Search ( HS) on CUDA for solving Traveling Salesman Problem ( TSP), which is an NP-hard problem in combinatorial optimization. the implementations are tested with data instances of varying problem size from TSPLIB to measure speedup attained over serial implementation. In our experiment, HSGPU parallel implementation can acquire 32 times speedup as compared with CPU- based implementation.

关键词： harmony search TSP GPU parallel processing

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parallel Execution of SVM Training using Graphics processing Units (SVMTrGPUs) 5

Parallel Execution of SVM Training using Graphics Processing...

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5th IEEE international conference on Control System, Computing and Engineering (ICCSCE)

作者： Salleh, Nur Shakirah Md Baharim, Muhammad Fahim Univ Tenaga Nas Dept Syst & Networking Shah Alam Selangor Malaysia

ISBN: (纸本)9781479982523

parallel computing is a simultaneous use of multiple compute resources, for example, processors to solve complex computational problems. It has been used in high-end computing areas such as pattern recognition, medical diagnosis, national defense, and web search engine. this paper focuses on the implementation of pattern classification technique, Support Vector Machine (SVM) using vector processor approach. We have carried out a performance analysis to benchmark the sequential SVM program against the Graphics processing Units (GPUs) optimization. the result shows that the parallelization of SVM training duration achieves a better performance than the sequential code speedups by 6.40.

关键词： parallel Computing Support Vector Machine CUDA Vector Processor Graphics processing Units UCW dataset

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A parallel Tabu Search Algorithm with Solution Space Partition for Cohesive Clustering Problems 15th

A Parallel Tabu Search Algorithm with Solution Space Partiti...

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15th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Xu, Zheng Cao, Buyang Tongji Univ Sch Software Engn Shanghai 201804 Peoples R China Tongji Univ China Intelligent Urbanizat Cocreat Ctr High Dens Shanghai 200092 Peoples R China

ISBN: (纸本)9783319271613;9783319271606

Clustering analysis plays an important role in a wide range of fields including data mining, pattern recognition, machine learning and many other areas. In this paper, we present a parallel tabu search algorithm for clustering problems. A permanent tabu list is proposed to partition the solution space for parallelization. Moreover, this permanent tabu list can also reduce the neighborhood space and constrain the election of candidates. the proposed approach is evaluated by clustering some specific dataset. And experimental results and speedups obtained show the efficiency of the parallel algorithm.

关键词： Combinatorial optimization Tabu search Clustering analysis parallel tabu search parallel clustering Solution space partition

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