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parallel implementation of dense optical flow computation on many-core processor 1

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Chen, Wenjie Yu, Jin Zhang, Weihua Jiang, Linhua Zhang, Guanhua Chai, Zhilei MoE Engineering Research Center for Software/Hardware Co-design Technology and Application East China Normal University Shanghai200061 China School of IoT Engineering Jiangnan University Wuxi214122 China Parallel Processing Institute Fudan University Shanghai200433 China Shanghai Key Lab of Modern Optical Systems University of Shanghai for Science and Technology Shanghai200093 China

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

Computation of optical flow is a fundamental step in computer vision applications. However, due to its high complexity, it is difficult to compute a high-accuracy optical flow field in real time. this paper proposes a parallel computing approach for fast computation of high-accuracy optical flow field. It is specially designed for Tilera, a typical many-core processor with 36 tiles. By efficiently exploiting the advantages of the mesh architecture of Tilera, and by appropriately handling the parallelism inherent in the optical flow computation, the proposed implemention is able to significantly reduce the computation time while keep a low power consumption. Experiment shows that, for a 640×480 image, the computation time is only 0. 80 seconds per frame. It is 2. 56 times faster than on a typical CPU i3-3240 (3. 4GHz), and the power consumption as less as 1/6. Experimental results also show that the proposed parallel approach is highly scalable for variable requirements on computation speeds and power consumptions, since it can flexibly selects a proper number of computing cores. © Springer international Publishing Switzerland 2015.

关键词： parallel processing systems

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Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT using 9/7 and 5/3 Filters 28

Low-Area and Low-Power Reconfigurable Architecture for Convo...

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28th international conference on VLSI Design (VLSID) / 14th international conference on Embedded Systems

作者： Meher, Pramod Kumar Mohanty, Basant Kumar Swamy, M. N. S. Nanyang Technol Univ Sch Comp Engn Nanyang Ave Singapore 639798 Singapore Jaypee Univ Engn & Technol Raghogarh Madhy Pradesh India Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 2W1 Canada

ISBN: (纸本)9781479966585

this paper presents an optimized adder-based formulation for low-area and low-power implementation of 1-D DWT using 5/3 and 9/7 filters. Not only the number of adders is minimized, the number bit-shifts also minimized in the formulation to reduce the bit-width of intermediate results. Separate Adder-based designs are derived using the proposed formulation for 9/7 filter, 5/3 filter and a reconfigurable structure for both 9/7 and 5/3 filters. the proposed structure for 9/7 filter requires 19 adders and 11 hardwired-shifters (shifters are implemented by rewiring only) and computes two DWT components in every clock cycle. It requires only 8 registers for two-stage pipeline implementation. the proposed reconfigurable structure involves a small overhead of complexity in terms of one adder, 2 MUXes, 2 registers, and 4 extra hardwired-shifters than the proposed 9/7 structure to have the reconfigurable design. the proposed reconfigurable structure supports higher usable frequency (without pipelining), and provides double the throughput per clock cycle compared to that of best available similar structure with marginally higher area complexity. ASIC synthesis results show that the proposed pipelined structure for 9/7 filters involves nearly 70% less ADP and 82% less EPO than the best of DA-based structures. Further, it involves less than half the ADP and 47% less EPO than the corresponding recent multiplier-based structure. the proposed reconfigurable structure involves less than one-third the EPO and ADP of similar existing structure. the proposed design indicates the superiority of adder-based design over DA-based design as well as conventional multiplier-based design.

关键词： adders application specific integrated circuits convolution discrete wavelet transforms distributed arithmetic high-pass filters low-pass filters low-power electronics reconfigurable architectures shift registers 5-3 filters 9-7 filters ADP ASIC synthesis DA-based structure design EPO MUX adder-based formulation design optimization bit-shift minimization clock cycle complexity overhead convolution-based 1-D DWT discrete wavelet transform hardwired-shifters high-pass filter higher usable frequency intermediate bit-width reduction low-area reconfigurable structure architecture low-pass filter low-power reconfigurable structure architecture multiplier-based structure design registers two-stage pipeline structure implementation Adders Clocks Discrete wavelet transforms Periodic structures Pipeline processing Registers throughput Discrete Wavelet Transform VLSI discrete wavelet transform adders distributed algorithms Registers Low pass filters clock cycle high-pass filters Pipeline processing application specific integrated circuits Reconfigurable architectures Convolution MULTIPLEXOR Adenosine Diphosphate Automatic data processing European Patent Office

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parallel bloom filter on xeon phi many-core processors 15th

Parallel bloom filter on xeon phi many-core processors

引用

15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Ni, Sheng Guo, Rentong Liao, Xiaofei Jin, Hai Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783319271217

Bloom filters are widely used in databases and network areas. these filters facilitate efficient membership checking with a low false positive ratio. It is a way to improve the throughput of bloom filter by parallel processing. Common many-core processors such as Xeon Phi can provide high parallelism. thus, we build an iterative model to analyze memory access performance. this performance suggests that the bottleneck in the traditional design is mainly caused by synchronization cost and memory latency on many-core platforms. therefore, we propose a parallel bloom filter (PBF), which is a lockless method involving input data preprocessing. this method reduces synchronization overhead and improves cache locality. We also implement and evaluate PBF on a Xeon Phi processor. Results show that the memory access performance is three times better than that of the counting bloom filter. PBF provides improved scalability, and the speedup ratio can reach a maximum of 80.7x. © Springer international Publishing Switzerland 2015.

关键词： Scalability

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In-Place Data Sliding algorithms for Many-Core architectures

In-Place Data Sliding Algorithms for Many-Core Architectures

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international conference on parallel processing (ICPP)

作者： Juan Gómez Gomez Luna Li-Wen Chang I-Jui Sung Wen-Mei Hwu Nicolás Guil Computer Architecture and Electronics University of Córdoba Córdoba Spain Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana Illinois USA MulticoreWare Inc. Champaign Illinois USA Computer Architecture University of Málaga Málaga Spain

In-place data manipulation is very desirable in many-core architectures with limited on-board memory. this paper deals with the in-place implementation of a class of primitives that perform data movements in one direction. We call these primitives Data Sliding (DS) algorithms. Notable among them are relational algebra primitives (such as select and unique), padding to insert empty elements in a data structure, and stream compaction to reduce memory requirements. their in-place implementation in a bulk synchronous parallel model, such as GPUs, is specially challenging due to the difficulties in synchronizing threads executing on different compute units. Using a novel adjacent work-group synchronization technique, we propose two algorithmic schemes for regular and irregular DS algorithms. With a set of 5 benchmarks, we validate our approaches and compare them to the state-of-the-art implementations of these benchmarks. Our regular DS algorithms demonstrate up to 9.11x and 73.25x on NVIDIA and AMD GPUs, respectively, the throughput of their competitors. Our irregular DS algorithms outperform NVIDIA thrust library by up to 3.24x on the three most recent generations of NVIDIA GPUs.

关键词： Synchronization Arrays Graphics processing units parallel processing Compaction Memory management

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Robust stereo matching using census cost, discontinuity-preserving disparity computation and view-consistent refinement 5

Robust stereo matching using census cost, discontinuity-pres...

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5th international conference on 3D Imaging, IC3D 2015

作者： Nguyen, Duc Minh Hanca, Jan Lu, Shao-Ping Munteanu, Adrian Department of Electronics and Informatics Pleinlaan 2 Brussels Belgium Department of Future Media and Imaging G. Crommenlaan 8 Ghent Belgium

ISBN: (纸本)9781509012657

Stereo matching has been one of the most active research topics in computer vision domain for many years resulting in a large number of techniques proposed in the literature. Nevertheless, improper combinations of available tools cannot fully utilize the advantages of each method and may even lower the performance of the stereo matching system. Moreover, state-of-the-art techniques are usually optimized to perform well on a certain input dataset. In this paper we propose a framework to combine existing tools into a stereo matching pipeline and three different architectures combining existing processing steps to build stereo matching systems which are not only accurate but also efficient and robust under different operating conditions. thorough experiments on three well-known datasets confirm the effectiveness of our proposed systems on any input data. © 2015 IEEE.

关键词： Stereo image processing

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30th international conference on High Performance Computing, ISC 2015

30th International Conference on High Performance Computing,...

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30th international conference on High Performance Computing, ISC 2015

the proceedings contain 37 papers. the special focus in this conference is on High Performance Computing. the topics include: Asynchronous Iterative Algorithm for Computing Incomplete Factorizations on GPUs;Matrix Multiplication on High-Density Multi-GPU architectures: theoretical and Experimental Investigations;A Framework for Batched and GPU-Resident Factorization algorithms Applied to Block Householder Transformations;parallel Efficient Sparse Matrix-Matrix Multiplication on Multicore Platforms;On the Design, Development, and Analysis of Optimized Matrix-Vector Multiplication Routines for Coprocessors;Large-Scale Neo-Heterogeneous Programming and Optimization of SNP Detection on Tianhe-2;ACCOLADES: A Scalable Workflow Framework for Large-Scale Simulation and Analyses of Automotive Engines;Accelerating LBM and LQCD Application Kernels by In-Memory processing;On Quantum Chemistry Code Adaptation for RSC PetaStream Architecture;Dtree: Dynamic Task Scheduling at Petascale;Feasibility Study of Porting a Particle Transport Code to FPGA;A Scalable, Linear-Time Dynamic Cutoff Algorithm for Molecular Dynamics;BWTCP: A parallel Method for Constructing BWT in Large Collection of Genomic Reads;Lattice-CSC: Optimizing and Building an Efficient Supercomputer for Lattice-QCD and to Achieve First Place in Green500;An Efficient Clique-Based Algorithm of Compute Nodes Allocation for In-memory Checkpoint System;A Scalable Algorithm for Radiative Heat Transfer Using Reverse Monte Carlo Ray Tracing;Optimizing Processes Mapping for Tasks with Non-uniform Data Exchange Run on Cluster with Different Interconnects;Striping Layout Aware Data Aggregation for High Performance I/O on a Lustre File System;Hop: Elastic Consistency for Exascale Data Stores;Energy-Efficient Data processing through Data Sparsing with Artifacts.

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A GPU based fast community detection implementation for social network 1

引用

15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Li, Guo Zhang, Dafang Xie, Kun Huang, Tanlong Li, Yanbiao College of Computer Science and Electronic Engineering Hunan University Changsha410082 China PLA 95874 Nanjing210016 China

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

Community structure represents a group of nodes which have similar characteristics in social network, so community detection is an important and popular work. However, community detection algorithms face the problem of low efficiency, due to complicated community definition and large amount of calculation. In order to implement efficient community detecting, we design Inner Outer Ratio (IOR) community metric, and propose Neighbor Compare Bidirectional Iteration (NCBI) detecting algorithm on GPU platform. IOR metirc uses (InnerEdges/InnerNodes)/(OuterEdges/OuterNodes) ratio for community structure definition. IOR metric only needs local network information and has a balanced consideration on both edges and nodes, and it is suit for high-performance parallel computing on GPU. NCBI algorithm adopts quick initialization mechanism through neighbor comparison, and uses bidirectional iteration to detect most probable communities based on IOR metric. To certify our community metric, we compare with traditional metrics including modularity and normal conductance. Experiment results show IOR metric is accuracy and works well in parallel computing, NCBI detecting algorithm is faster based on GPU accelerating platform. © Springer international Publishing Switzerland 2015.

关键词： Graphics processing unit

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parallel training GBRT based on Kmeans histogram approximation for big data 15th

Parallel training GBRT based on Kmeans histogram approximati...

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Gu, Rong Jin, Lei Wu, Yongwei Qu, Jingying Wang, Tao Wang, Xiaojun Yuan, Chunfeng Huang, Yihua National Key Laboratory for Novel Software Technology Collaborative Innovation Center of Novel Software Technology and Industrialization Nanjing University Nanjing210023 China Baidu Inc. Beijing100085 China

ISBN: (纸本)9783319271217

Gradient Boosting Regression Tree (GBRT), one of the stateof- the-art ranking algorithms widely used in industry, faces challenges in the big data era. With the rapid increase in the sizes of datasets, the iterative training process of GBRT becomes very time-consuming over large scale data. In this paper, we aim to speed up the training process of each tree in the GBRT framework. First, we propose a novel KMeans histogram building algorithm which has lower time complexity and is more efficient than the cutting-edge histogram building method. Further, we put forward an approximation algorithm by combining the kernel density estimation with the histogram technique to improve the accuracy. We conduct a variety of experiments on both the public Learning To Rank(LTR) benchmark datasets and the large-scale real-world datasets from Baidu search engine. the experimental results show that our proposed parallel training algorithm outperforms the state-of-the-art parallel GBRT algorithm with near 2 times speedup and better accuracy. Also, our algorithm achieves the near-linear scalability. © Springer international Publishing Switzerland 2015.

关键词： Search engines

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A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter

A parallel luma-chroma filtering architecture for H.264/AVC ...

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IEEE international conference on Consumer Electronics - Berlin (ICCE-Berlin)

作者： Nikolaos Kefalas George theodoridis ECE Department University of Patras Patras Greece

A novel architecture for the H.264/AVC deblocking filter is proposed. It includes three filtering units to filter in parallel the luma and chroma components. Also, a proper two dimensional filtering order for the luma edges and a one-dimensional filtering order for the chroma edges are presented. the architecture achieves 750 MHz in 560 MHz in 90nm and 130 nm, respectively, and requires 76 cycles to filter each MB. Compared to existing architectures, it outperforms them in frequency and throughput, while it is the only one that achieves over 60 Fps in 8K-UHD resolution.

关键词： Filtering Pipelines Filtering algorithms Engines Organizations Standards throughput

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DFIS: A scalable distributed fingerprint identification system 15th

DFIS: A scalable distributed fingerprint identification syst...

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Zhao, Yunxiang Zhang, Wanxin Li, Dongsheng Huang, Zhen National Laboratory for Parallel and Distributed Processing College of Computer National University of Defence Technology ChangshaHunan410073 China

ISBN: (纸本)9783319271361

Fingerprint has been widely used in a variety of biometric identification systems. However, with the rapid development of fingerprint identification systems, the amount of fingerprints information stored in systems has been rising sharply, making it challenging to process and store fingerprints efficiently and robustly with traditional standalone systems and relational databases. In this paper, we propose a scalable distributed fingerprint identification system, named DFIS. It combines the feature extraction procedure with HIPI library and optimizes the load balance strategy of MongoDB to construct a much more robust and stable system. Related experiments and simulations have been carried out and results show that DFIS can reduce the time expense by 70% during the features extraction procedural. For load balance of MongoDB, DFIS can decrease the difference of access load to less than 5% and meanwhile decrease 50% data migration to gain more reasonable distribution of operation load and data load among shards compared with the default load balance strategy in MongoDB. © Springer international Publishing Switzerland 2015.

关键词： Distributed computer systems

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