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Program slicing based on runtime dataflow measurements

Program slicing based on runtime dataflow measurements

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international Carpathian Control conference (ICCC)

作者： Gábor Wacha János Lazányi Béla Fehér Department of Measurement and Information Technology Budapest University of Technology and Economics Budapest Hungary

Multicore architectures enable increasing the performance of the system with parallel processing. One of the challenges of a multicore embedded system is the correct usage of the processor cores. It is possible to achieve balanced processor load on the different cores, but the communication bandwidth between the cores is often a bottleneck. Passing large amounts of data between tasks mapped to different processor cores can result in cache misses in the local cache of a processor core. this paper introduces an analyzation method based on runtime generated data flow graphs to find the data paths of an algorithm. It shows that a spectral cluster analysis can help to discover data independent subsets in the algorithm under test. Finding the data independent parts helps to partition the program to multiple slices where the inter-slice communication is kept as low as possible. With our proposed method the communication bottleneck can be evaded in a multicore, multitask implementation, possibly resulting in better performance.

关键词： Multicore processing Clustering algorithms Algorithm design and analysis Software Runtime Software algorithms Symmetric matrices

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A novel search engine-based method for discovering command and control server 15th

A novel search engine-based method for discovering command a...

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Guo, Xiaojun Cheng, Guang Pan, Wubin Dinhtu, Truong Liang, Yixin School of Computer Science and Engineering Southeast University Nanjing211189 China Key Laboratory of Computer Network and Information Integration Southeast University Nanjing211189 China School of Information Engineering Xizang Minzu University Xianyang712082 China XiZang Key Laboratory of Optical Information Processing and Visualization Technology Xizang Minzu University Xianyang712082 China

ISBN: (纸本)9783319271361

To solve the problem of getting command and control (C&C) server address covertly for malware of Botnet or advanced persistent threats, we propose a novel C&C-server address discovery scheme via search engine. this scheme is com-posed of five modules. the botmaster uses publish module to issue C&C-server IPs in diaries of several free blogs on Internet firstly. then these diaries could be indexed by search engine (SE). When the infected terminal becomes a bot, it uses keyword production module to produce search keyword and submits some or all these keywords to SEs to obtain the search engine result pages (SERPs). For items in SERPs, the bot uses filtering algorithm to remove noise items and leave valid items whose abstract contain C&C-server IPs. Lastly the bot utilizes extraction and conversion module to extract these C&C-server IPs and translates them into binary format. the experimental results show that our proposed scheme is fully able to discover and obtain C&C-server IPs via various search engines. Furthermore, if we set proper threshold value for SE, it can extract C&C-server IPs accurately and efficiently. © Springer international Publishing Switzerland 2015.

关键词： Search engines

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Completion time-a ware flow scheduling in heterogenous networks 1

引用

15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： He, Shiming Xie, Kun Zhang, Dafang Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation School of Computer and Communication Engineering Hunan Province Engineering Research Center of Electric Transportation and Smart Distributed Network Changsha University of Science and Technology Changsha410114 China College of Computer Science and Electronics Engineering Hunan University Changsha410082 China Department of Electrical and Computer Engineering State University of New York at Stony Brook NY United States

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

In China, the expressway isn’t free. When a vehicle exits, the exit toll station needs to calculate the toll according to the vehicle trajectory obtained by sending a trajectory query task to the trajectory center remotely. For the accurate of toll and keep the exit smoothly, transmitting the trajectory result reliably and in time is a key issue. there are three heterogenous networks in expressway, Fibernet, Telecommunications Network and 3G. We concurrently exploit three heterogenous networks by allocating the trajectory result into three sub-flows where each sub-flow is transmitted in one kind of networks. But existing multipath transfer solution(FMTCP) doesn’t consider the difference of completed time among all sub-flows and can’t make sure the completed time in time. therefore, we formulate the sub-flows schedule as a integer programming problem, which is proved to be NP-hard problem, and propose a Completion time-aware Flow Scheduling scheme (CaFS) which calculates the size of sub-flows. For the reliably, it exploits generation-based network coding. For the transmission in time, CaFS allocates the size of sub-flow into suitable generation and scheduling the generations. the simulation results demonstrate that, comparing with the FMTCP, CaFS improves 31. 9% in completion time and 30% in task finished rate. © Springer international Publishing Switzerland 2015.

关键词： Network coding

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Composite behaviors of series and parallel meminductor circuits

Composite behaviors of series and parallel meminductor circu...

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international conference on Information Science and Technology (ICIST)

作者： Hairui Yao Shukai Duan Lidan Wang College of Electronics and Information Engineering Southwest University Chongqing China

Meminductor generated on the basis of the conception of a memristor has many promising characteristics, such as analog processing capacity, storing energy and operating as non-volatile memories with essentially lossless data reading and storing, etc. [1] However, there are few studies about meminductor's applications due to the unavailability of solid-state meminductor and composite behaviors of multiple meminductor series-parallel circuits are not fully understood. In this paper, we investigate the composite characteristics of multiple meminductor circuits via the relationships among charge, the time integral of flux and meminductance of each meminductor and composite device. Furthermore, a general computing method of composite meminductance for multiple meminductor circuits is proposed. the results of this study can be used to construct composite meminductor circuits with complex characteristics and have promising applications in the non-volatile memory circuits.

关键词： Indexes

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Evaluation of global synchronization for iterative algebra algorithms on many-core

Evaluation of global synchronization for iterative algebra a...

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ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing (SNPD)

作者： Ayaz ul Hasan Khan Mayez Al-Mouhamed Lutfi A. Firdaus Department of Computer Engineering College of Computer Science & Engineering Dhahran Saudi Arabia

Massively parallel computing is applied extensively in various scientific and engineering domains. With the growing interest in many-core architectures and due to the lack of explicit support for inter-block synchronization specifically in GPUs, synchronization becomes necessary to minimize inter-block communication time. In this paper, we have proposed two new inter-block synchronization techniques: 1) Relaxed Synchronization, and 2) Block-Query Synchronization. these schemes are used in implementing numerical iterative solvers where computation/communication overlapping is one used optimization to enhance application performance. We have evaluated and analyzed the performance of the proposed synchronization techniques using Jacobi Iterative Solver in comparison to the state of the art inter-block lock-free synchronization techniques. We have achieved about 1-8% performance improvement in terms of execution time over lock-free synchronization depending on the problem size and the number of thread blocks. We have also evaluated the proposed algorithm on GPU and MIC architectures and obtained about 8-26% performance improvement over the barrier synchronization available in OpenMP programming environment depending on the problem size and number of cores used.

关键词： Synchronization Graphics processing units Jacobian matrices Instruction sets Kernel Computer architecture Microwave integrated circuits

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Improving coverage of rule based NER systems

Improving coverage of rule based NER systems

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international conference on Information and Communication Technology and Accessibility (ICTA)

作者： Emna Hkiri Souheyl Mallat Mounir Zrigui Faculty of sciences of Monastir

Named entity recognition (NER) is the problem of identifying (locating and categorizing) atomic entities in a given text that fall into predefined categories or classes. In this work, we developed a bilingual Arabic-English lexicon of named entities (NE) to improve the performance of Arabic rule-based systems. To reach our goal, we followed different steps starting by the pre-editing of the DBpedia linked data entities and the parallel corpus and then applying our automatic model for detection, extraction and translation of Arabic-English Named Entities. Our approach is fully automatic and hybrid, it combines linguistic and statistical methods.

关键词： Organizations Logic gates Natural language processing Training Data mining Pragmatics Text recognition

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A Data-Oriented Method for Scheduling Dependent Tasks on High-Density Multi-GPU Systems

A Data-Oriented Method for Scheduling Dependent Tasks on Hig...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Peng Zhang Yuxiang Gao Meikang Qiu Biomedical Engineering Department Stony Brook University Stony Brook NY United States Cluster Solution Department Cray Inc. San Jose CA United States Computer Science Department Pace University New York NY United States

ISBN: (纸本)9781479989386

the rapidly-changing computer architectures, though improving the performance of computers, have been challenging the programming environments for efficiently harnessing the potential of novel architectures. In this area, though the high-density multi-GPU architecture enabled unparalleled performance advantage of dense GPUs in a single server, it has increased the difficulty for scheduling diversified and dependent tasks. We therefore propose a data-oriented method for scheduling dependent tasks for this architecture while providing its implementation. In our method, we model a parallel program as a collection of data-dependent tasks for which data dependencies are managed by an expressive matrix. Accordingly, we develop a hierarchical scheduler infrastructure for our model. In this, a top scheduler is built for querying the data-dependency matrix; three downstream schedulers for queuing computation tasks that are exclusively assigned to processor, accelerator or either; and a multitude of bottom schedulers each for providing a processing element with assigned tasks. We experiment our scheduler for examples of Strassen matrix multiplication and Cholesky matrix inversion algorithms on a computer that has 8 Tesla K40 GPUs. the results show that our method is capable of offering the efficient task parallelism while fulfilling the complex task dependencies. When advanced task-oriented schedulers have been widely designed for distributed systems, a lightweight data-driven scheduler could be an alternative and handy approach that can handle the dependent yet diversified tasks of data-intensive applications for the novel high-density multi-accelerator system.

关键词： Computer architecture Processor scheduling Computers Symmetric matrices Partitioning algorithms Runtime Graphics processing units

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Textured beta-sialon: Eu2+ phosphor deposits fabricated by electrophoretic deposition (EPD) process within a strong magnetic field: Preparation process and photoluminescence (PL) properties depending on orientation 5th

Textured beta-sialon: Eu2+ phosphor deposits fabricated by e...

引用

5th international conference on Electrophoretic Deposition: Fundamentals and Applications, EPD 2014

作者： Zhang, Chenning Uchikoshi, Tetsuo Liu, Lihong Dierre, Benjamin Cho, Yujin Sakka, Yoshio Hirosaki, Naoto Sekiguchi, Takashi Materials Processing Unit National Institute for Materials Science Tsukuba Ibaraki305-0047 Japan Sialon Unit National Institute for Materials Science Tsukuba Ibaraki305-0044 Japan Nano-Electronics Materials Unit National Institute for Materials Science Tsukuba Ibaraki305-0044 Japan

ISBN: (纸本)9783038354970

Beta-sialon:Eu2+ phosphor deposits were fabricated by electrophoretic deposition (EPD) process within a strong magnetic field (12 T). the direction of the magnetic field was adjusted to be parallel or perpendicular to that of the electric field, that is, vertical- or horizontal setup. the oriented deposits were fabricated by aligning the ß-sialon:Eu2+ particles along the higher magnetic-susceptibility c-crystal axis (a, b-crystal plane). For the case of vertically-setup magnetic field, the oriented deposit aligned along the c-axis possessed higher relative deposit density than the randomly fabricated deposit, as a result, varying the intensity ratio of emission and transmitted excitation, and therefore, presenting different chromaticity coordinates;for the case of horizontally-setup magnetic field, photoluminescence (PL) intensities of the deposits oriented along c-axis were significantly improved by comparing with those of the randomly-oriented ones. © (2015) Trans Tech Publications, Switzerland.

关键词： Deposits

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A high-performance Click-based packet classifier on GPU

A high-performance Click-based packet classifier on GPU

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international econference on Computer and Knowledge Engineering (ICCKE)

作者： Maisam Gholami Younes Sookhtezari Milad Haghighi Bahram BahramBeigy Mahmood Ahmadi Information Technology Department Islamic Azad University of Kermanshah Kermanshah Iran Computer Engineering Department Razi University Kermanshah Iran

In this paper, design and configuration of a high-performance Click-based packet classifier on GPU is presented. In this regard, Bloom filter-based classification algorithm is used in order to design and implement the Click-based packet classifier elements (processors) on Graphics processing Unit (GPU). On one hand, utilization of Bloom filter data structure leads to memory usage reduction of the router. On the other hand, the parallel nature of Bloom filter and GPU architecture bring higher throughput of the software router. the analysis results indicate approximately five times speedup of the proposed Click-based classifier on GPU compared with the standard Click-based classifier.

关键词： Graphics processing units Indexes Arrays

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Accelerating 3D Digital Differential Analyzer Ray Tracing Algorithm on the GPU Using CUDA

Accelerating 3D Digital Differential Analyzer Ray Tracing Al...

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international conference on parallel processing Workshops (ICPPW)

作者： Yan Li Hongyu Sun Jingchao Yuan Ting Wu Yanshan Tian Yanlin Li Rui Zhou Kuan-Ching Li School of Information Science and Engineering Lanzhou University Lanzhou China Manthematic and Computer Science Department Ningxia Normal University Guyuan China Chinese Academy of Sciences Institute of Modern Physics Lanzhou Gansu China Dept. of Computer Science and Information Engr. Providence University Taichung Taiwan

We present a novel optimized 3DDDA ray tracing algorithm on GPUs with CUDA architecture. the grid data is built on the host and then copied to the device. the whole traversing procedure is done on the GPU device. So it just needs the data transformation between the host and the device once. the results show that the CUDA implementation parallel code using different block size on GPU achieves 2.9x to 5.9x faster speed compared with the CPU implementation. And the performance is significantly influenced by the size of the CUDA block. 3DDDA algorithm on CUDA architecture can really get the performance accelerated with a reasonable block size, but it is difficult to play high-end GPU performance. the main reason is that 3DDDA algorithm for memory access is discontinuous, so it is difficult to play high-frequency performance of RAM DDR5.

关键词： Graphics processing units Ray tracing Partitioning algorithms Acceleration parallel processing Computer architecture Software algorithms

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