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DIRECT NUMERICAL SIMULATION OF TURBULENT FLOWS WIth parallel algorithms FOR VARIOUS COMPUTING architectures 11

DIRECT NUMERICAL SIMULATION OF TURBULENT FLOWS WITH PARALLEL...

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11th World Congress on Computational Mechanics (WCCM) / 5th European conference on Computational Mechanics (ECCM) / 6th European conference on Computational Fluid Dynamics (ECFD)

作者： Gorobets, A. Trias, F. X. Borrell, R. Oyarzun, G. Oliva, A. Tech Univ Catalonia ETSEIAT Heat & Mass Transfer Technol Ctr C Colom 11 Terrassa 08222 Spain Russian Acad Sci Keldysh Inst Appl Math Moscow 125047 Russia Termo Fluids SL Sabadell 08204 Barcelona Spain

ISBN: (纸本)9788494284472

the purpose of the work is twofold. Firstly, it is devoted to the development of efficient parallel algorithms for large-scale simulations of turbulent flows on different supercomputer architectures. It reports experience with massively-parallel accelerators including graphics processing units of AMD and NVIDIA and Intel Xeon Phi coprocessors. Secondly, it introduces new series of direct numerical simulations of incompressible turbulent flows with heat transfer performed with the considered algorithms.

关键词： parallel CFD turbulent flows MPI OpenMP OpenCL

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parallel aware hybrid Solid-State storage 15th

Parallel aware hybrid Solid-State storage

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： He, Dan Wang, Fang Feng, Dan Liu, Jingning Wu, Yunxiang He, Ying Hu, Yang Wuhan National Laboratory for Optoelectronics School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Nanchang Hangkong University Nanchang330063 China China Ship Development and Design Center Wuhan430064 China

ISBN: (纸本)9783319271392

Compared with tradition disk, NAND Flash has advantages of higher performance and shock resistance. But before write, NAND Flash must erase the old messages. that why NAND Flash based Solid State Disks (SSDs) always use the log-based schemes to improve the performance. Compared with NAND Flash, Phase Change Memory (PCM) has higher write performance, longer lifetime, and can update in-place, but its cost is high and capacity is low. So, in PCM and NAND Flash hybrid SSD, PCM is always used as log region, such as In-Page Logging-based (hybrid-IPL) SSD. the log-based SSD incurs a large number of merge operations. the cost of merge operation is very high because it involves many read, write operations, as well as an erase operation. So, how to reduce the cost of merge operations is the critical challenge to log-based hybrid (PCM and flash) SSD. In this paper, we propose a new merge scheme in PCM and NAND Flash hybrid SSD, called parallel aware hybrid In-Page Logging-based (P-aware-IPL) SSD. this scheme can exploit the die-level and plane-level parallelism of flash. Leveraging these two levels of parallelism, the cost of full merge is significantly reduced compared with that of hybrid-IPL SSD scheme and there is no other additional overhead in our algorithm. Experiment results have shown that the proposed P-aware-IPL reduces the flash write and erase operations by up to 10% and average response time by up to 22% against the hybrid-IPL scheme. © Springer international Publishing Switzerland 2015.

关键词： Cost reduction

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Efficient Cryptology-Specific Instructions Generation with Algebra Primitives

Efficient Cryptology-Specific Instructions Generation with A...

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Lei Liu Guijie Han Zixin Zhou Sikun Li Department of Electronics Officers College Of Chinese Armed Police Force Cheng Du China School of Computer Science National University of Defense Technology Chang Sha China

ISBN: (纸本)9781467394741

this paper presents a novel approach for cryptology-specific instructions generation on a reconfigurable architecture which is named ASRA. the ASRA tightly integrates a customized reconfigurable core with a very-long instruction word basic core. Both cores in ASRA can work in parallel. the methodology for cryptology-specific instruction generation can directly deploy algebraic operations as primitives for ASRA's custom function units (CFUs), and is able to eliminate a large portion of design space exploration difficulty from conventional data-flow graph methods. Cryptology-specific instructions for block cipher and hash algorithms which are kernel data processing tasks in security applications are exploited. then an accelerator prototype of the ASRA is built on a Xilinx Kintex-7 FPGA chip. Experiment results show that our work achieves a high performance improvement and a good flexibility.

关键词： Cryptography Hardware Registers Reconfigurable architectures Fabrics Algebra

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A hybrid genetic algorithm for privacy and cost aware scheduling of data intensive workflow in cloud 1

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Chen, Congyang Liu, Jianxun Wen, Yiping Chen, Jinjun Zhou, Dong Key Laboratory of Knowledge Processing and Networked Manufacture Hunan University of Science and Technology Xiangtan411100 China College of Computer Science and Engineering Hunan University of Science and Technology Xiangtan411100 China University of Technology Sydney UltimoNSW2070 Australia

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

In the context of cloud computing and big data, the data of all walks of life has been obtained conveniently. Some information of users in the business process is in need of protection with the popularity of workflow applications, which will greatly affect the scheduling of workflow. Meanwhile, the amount of data is usually very large in workflow, the data privacy protection in workflow has also become an important research problem. In this paper, in order to satisfy the requirement of data privacy protection from user and minimize the total scheduling cost in workflow scheduling, we proposed a privacy and cost aware method based on genetic algorithm for data intensive workflow applications which takes into account computation cost, data transmission cost and data storage cost in cloud to solve this problem on finding the best scheduling solution. the proposed algorithm uses the summation of upward and downward rank values for prioritizing workflow tasks, then merges it to make an optimal initial population to obtain a good solution quickly. Besides, a series of operations like selection, crossover and mutation have been used to optimize the scheduling. In the workflow task scheduling, we assign the datacenter for tasks needing privacy protection, which data of these tasks cannot be moved or copied to other datacenter. Finally, we demonstrate the potential of proposed algorithm for optimizing economic cost with user privacy protection requirement. the experimental results show that proposed algorithm can help improve the scheduling and save the time and cost by an average of 3. 6% and 15. 6% respectively. © Springer international Publishing Switzerland 2015.

关键词： Scheduling

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A Framework for Batched and GPU-Resident Factorization algorithms Applied to Block Householder Transformations 1

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30th international Supercomputing conference on High Performance Computing (ISC High Performance)

作者： Haidar, Azzam Dong, Tingxing Tim Tomov, Stanimire Luszczek, Piotr Dongarra, Jack Univ Tennessee Knoxville TN 37916 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester Lancs England

ISBN: (数字)9783319201191

ISBN: (纸本)9783319201191;9783319201184

As modern hardware keeps evolving, an increasingly effective approach to developing energy efficient and high-performance solvers is to design them to work on many small size and independent problems. Many applications already need this functionality, especially for GPUs, which are currently known to be about four to five times more energy efficient than multicore CPUs. We describe the development of one-sided factorizations that work for a set of small dense matrices in parallel, and we illustrate our techniques on the QR factorization based on Householder transformations. We refer to this mode of operation as a batched factorization. Our approach is based on representing the algorithms as a sequence of batched BLAS routines for GPU-only execution. this is in contrast to the hybrid CPU-GPU algorithms that rely heavily on using the multicore CPU for specific parts of the workload. But for a system to benefit fully from the GPU's significantly higher energy efficiency, avoiding the use of the multicore CPU must be a primary design goal, so the system can rely more heavily on the more efficient GPU. Additionally, this will result in the removal of the costly CPU-to-GPU communication. Furthermore, we do not use a single symmetric multiprocessor(on the GPU) to factorize a single problem at a time. We illustrate how our performance analysis, and the use of profiling and tracing tools, guided the development and optimization of our batched factorization to achieve up to a 2-fold speedup and a 3-fold energy efficiency improvement compared to our highly optimized batched CPU implementations based on the MKL library(when using two sockets of Intel Sandy Bridge CPUs). Compared to a batched QR factorization featured in the CUBLAS library for GPUs, we achieved up to 5x speedup on the K40 GPU.

关键词： Graphics processing unit

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pDindel: Accelerating indel detection on a multicore CPU architecture with SIMD

pDindel: Accelerating indel detection on a multicore CPU arc...

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IEEE international conference on Computational Advances in Bio and Medical Sciences (ICCABS)

作者： Da Zhang Hao Wang Kaixi Hou Jing Zhang Wu-chun Feng Department of Computer Science Virginia Tech Blacksburg Virginia USA

ISBN: (纸本)9781467396646

Small insertions and deletions (indels) of bases in the DNA of an organism can map to functionally important sites in human genes, for example, and in turn, influence human traits and diseases. Dindel detects such indels, particularly small indels (> 50 nucleotides), from short-read data by using a Bayesian approach. Due to its high sensitivity to detect small indels, Dindel has been adopted by many bioinformatics projects, e.g., the 1,000 Genomes Project, despite its pedestrian performance. In this paper, we first analyze and characterize the current version of Dindel to identify performance bottlenecks. We then design, implement, and optimize a parallelized Dindel (pDindel) for a multicore CPU architecture by exploiting thread-level parallelism (TLP) and data-level parallelism (DLP). Our optimized pDindel can achieve up to a 37-fold speedup for the computational part of Dindel and a 9-fold speedup for the overall execution time over the current version of Dindel.

关键词： Genomics Sequential analysis parallel processing Multicore processing Bayes methods DNA Sensitivity

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Performance improvement of data mining in Weka through GPU acceleration

Performance improvement of data mining in Weka through GPU a...

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5th international conference on Ambient Systems, Networks and Technologies (ANT) / 4th international conference on Sustainable Energy Information Technology (SEIT)

作者： Engel, Tiago Augusto Charao, Andrea Schwertner Kirsch-Pinheiro, Manuele Steffenel, Luiz-Angelo Univ Fed Santa Maria BR-97119900 Santa Maria RS Brazil Univ Paris 01 F-75231 Paris 05 France Univ Reims Reims France

Data mining tools may be computationally demanding, so there is an increasing interest on parallel computing strategies to improve their performance. the popularization of Graphics processing Units GPUs) increased the computing power of current desktop computers, but desktop-based data mining tools do not usually take full advantage of these architectures. this paper exploits an approach to improve the performance of Weka, a popular data mining tool, through parallelization on GPU-accelerated machines. From the profiling of Weka object-oriented code, we chose to parallelize a matrix multiplication method using state-of-the-art tools. the implementation was merged into Weka so that we could analyze the impact of parallel execution on its performance. the results show a significant speedup on the target parallel architectures, compared to the original, sequential Weka code. (C) 2014 the Authors. Published by Elsevier B.V.

关键词： data mining tools parallel computing GPU

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A design of a GP-GPU based stream processor for an image processing

A design of a GP-GPU based stream processor for an image pro...

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international conference on Telecommunications and Signal processing (TSP)

作者： Kwang Yeob Lee Gyutaek Kyung Tae Ryong Park Jae Chang Kwak Yong Seo Koo Department of Computer Engineering Seokyeong University Seoul Korea NEXTCHIP co. Ltd Korea Department of Computer Science Seokyeong University Seoul Korea Department of Electronics Engineering Dankook University Korea

ISBN: (纸本)9781479984992

Mobile devices provide a more realistic image processing and various high spec features to satisfy users. So, mobile devices have been developing in the direction of computing acceleration by using a strong parallelism of GP-GPU processing. In this paper, a GP-GPU architecture is proposed based on stream processing architecture which has the advantage of high parallelism to enhance the image processing capability. the proposed GP-GPU architecture consists of 8 stream processors and has multi-banked cache memory structure. the results of verification shows that the proposed stream processor improves the performance of the integral image generation : 24.5%, 3×3 Gaussian filer mask : 4.7%, 5×5 Gaussian filter mask : 1.3% in comparison with ARM Cortex-A15 quad core.

关键词： Instruction sets Computer architecture parallel processing Image processing Cache memory Indexes Filtering algorithms

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Performance Characterization and Evaluation of HPC algorithms on Dissimilar Multicore architectures 16

Performance Characterization and Evaluation of HPC Algorithm...

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16th IEEE international conference on High Performance Computing and Communications HPCC 2014\11th IEEE international conference on Embedded Software and Systems ICESS 2014\6th international Symposium on Cyberspace Safety and Security CSS 2014

作者： Krishnan, S. P. T. Veeravalli, Bharadwaj Agcy Sci Technol & Res Inst Infocomm Res Singapore 138632 Singapore Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore

ISBN: (纸本)9781479961238

In this paper, we share our experiences in using two important yet different High Performance Computing (HPC) architectures for evaluating two HPC algorithms. the first architecture is an Intel x64 ISA based homogenous multicore with Uniform Memory Access (UMA) type shared-memory based Symmetric Multi-processing system. the second architecture is an IBM Power ISA based heterogenous multicore with Non-Uniform Memory Access (NUMA) based distributed-memory Asymmetric Multi-processing system. the two HPC algorithms are for predicting biological molecular structures, specifically the RNA secondary structures. the first algorithm that we created is a parallelized version of a popular serial RNA secondary structure prediction algorithm called PKNOTS. the second algorithm is a new parallel-by-design algorithm that we have developed called MARSs. Using real Ribo-Nucleic Acid (RNA) sequences, we conducted large-scale experiments involving hundreds of sequences using the above two algorithms. Based on thousands of data points that we collected as an outcome of our experiments, we report on the observed performance metrics for both the algorithms on the two architectures. through our experiments, we infer that architectures with specialized co-processors for number-crunching along with high-speed memory bus and dedicated bus controllers generally perform better than general-purpose multi-processor architectures. In addition, we observed that algorithms that are intrinsically parallelized by design are able to scale & perform better by taking advantage of the underlying parallel architecture. We further share best practices on handling scalability aspects with regards to workload size. We believe our results are applicable to other HPC applications on similar HPC architectures.

关键词： ARCHITECTURE High Performance Computing algorithms Multi-core processors Prediction algorithms parallel architectures Multi-processing Performance metrics Building construction Best Practices

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Optimized Password Recovery for Encrypted RAR on GPUs

Optimized Password Recovery for Encrypted RAR on GPUs

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Xiaojing An Haipeng Jia Yunquan Zhang Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479989386

Files are often compressed for efficiency. RAR is a common archive file format that supports data compression, error recovery and file spanning. RAR uses classic symmetric encryption algorithm SHA-1 hashing and AES algorithm for encryption. these two algorithms cannot be cracked, so the only method of password recovery is brute force, which is very time-consuming. In this paper, we present an approach using GPUs to speed up the password recovery process. However, because the major calculation and time-consuming part, SHA-1 hashing, is hard to be parallelized, so this paper adopts coarse granularity parallel. that is, one GPU thread is responsible for the validation of one password. We mainly use four optimization methods to optimize this parallel version: asynchronous parallel between CPU and GPU, redundant calculations and conditional statements reduction, data locality by using LDS, and the usage of registers optimization. Experiment result shows that the final version reaches 43~57 times speedup on an AMD FirePro W8000 GPU, compared to a well-optimized serial version on Intel Core i5 CPU. Meanwhile, linear performance acceleration is achieved when using multi-GPUs.

关键词： Graphics processing units Registers Force Optimization Encryption Algorithm design and analysis

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