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Accelerating Rabin Karp on a Graphics processing Unit (GPU) using Compute Unified Device Architecture (CUDA) 7

Accelerating Rabin Karp on a Graphics Processing Unit (GPU) ...

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2014 7th international conference on Information and Automation for Sustainability, ICIAfS 2014

作者： Dayarathne, Nayomi Ragel, Roshan University of Peradeniya Sri Lanka

ISBN: (纸本)9781479945986

String matching or pattern matching algorithms are used in various applications. they are used to find the occurrences of a pattern in a given text or a pool of strings. they are widely used in text editors in computing machines, database queries, bio-informatics, chem-informatics, search engines and many more applications. String matching algorithms can be of two ways: single pattern matching and multiple pattern matching. Rabin Karp is a string searching algorithm that can act in both ways. Since these algorithms are working on large pool of data, achieving higher throughput on the implementation of the algorithm has always been a major concern. parallel implementation of such algorithms can achieve the concerned objective. parallelism could be achieved easily with the rapid development of GPU architectures. In this research, Rabin Karp algorithm is implemented in CUDA C. We have compared CUDA implementation of this algorithm against both its serial CPU implementation and parallel Pthread implementation on multi-core CPUs. Eventually, using the empirical results, we could conclude that the CUDA C implementation of Rabin Karp on the GPU can achieve much high throughput for a large pool of data in string matching. © 2014 IEEE.

关键词： Graphics processing unit

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FEVES: Framework for Efficient parallel Video Encoding on Heterogeneous Systems 43

FEVES: Framework for Efficient Parallel Video Encoding on He...

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43rd Annual international conference on parallel processing (ICPP)

作者： Ilic, Aleksandar Momcilovic, Svetislav Roma, Nuno Sousa, Leonel Univ Lisbon INESC ID IST Lisbon Portugal

ISBN: (纸本)9781479956180

Lead by high performance computing potential of modern heterogeneous desktop systems and predominance of video content in general applications, we propose herein an autonomous unified video encoding framework for hybrid multi-core CPU and multi-GPU platforms. To fully exploit the capabilities of these platforms, the proposed framework integrates simultaneous execution control, automatic data access management, and adaptive scheduling and load balancing strategies to deal with the overall complexity of the video encoding procedure. these strategies consider the collaborative inter-loop encoding as a unified optimization problem to efficiently exploit several levels of concurrency between computation and communication. To support a wide range of CPU and GPU architectures, a specific encoding library is developed with highly optimized algorithms for all inter-loop modules. the obtained experimental results show that the proposed framework allows achieving a real-time encoding of full high-definition sequences in the state-of-the-art CPU+GPU systems, by outperforming individual GPU and quad-core CPU executions for more than 2 and 5 times, respectively.

关键词： Video Coding Heterogeneous Systems GPGPU Load Balancing

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20th international conference on parallel processing, Euro-Par 2014

20th International Conference on Parallel Processing, Euro-P...

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20th international conference on parallel processing, Euro-Par 2014

ISBN: (纸本)9783319098722

the proceedings contain 68 papers. the special focus in this conference is on Support tools environments, Performance prediction and evaluation, Scheduling and load balancing, High performance architectures and compilers, parallel and distributed data management, Grid, Cluster and cloud computing, Green high performance computing, Distributed systems and algorithms, parallel and distributed programming, parallel numerical algorithms, Multicore and manycore programming, theory and algorithms for parallel computation and High performance networks and communication. the topics include: MPI trace compression using event flow graphs;customized scalable tracing with in-situ data analysis;performance measurement and analysis of transactional memory and speculative execution on IBM blue Gene/Q;an open-source management framework for cloud applications;modeling and simulation of a dynamic task-based runtime system for heterogeneous multi-core architectures;modeling the impact of reduced memory bandwidth on HPC applications;finding the important basic blocks in multithreaded programs;optimization and trade-off analysis for time, energy and resource usage;performance prediction and evaluation of parallel applications in KVM, Xen, and VMware;per-task DRAM energy metering in multicore systems;characterizing the performance-energy tradeoff of small ARM cores in HPC computation;finding efficient queue setup using high-resolution simulations;a progressively pessimistic scheduler for software transactional memory;a queueing theory approach to pareto optimal bags-of-tasks scheduling on clouds;scheduling/placement approach for task-graphs on heterogeneous architecture;energy-aware multi-organization scheduling problem;energy efficient scheduling of mapreduce jobs and switchable scheduling for runtime adaptation of optimization.

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Video processing on GPU: Analysis of data transfer overhead 26

Video processing on GPU: Analysis of data transfer overhead

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26th IEEE international Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014

作者： Prata, Renan Bentes, Cristiana Farias, Ricardo Department of System Engineering State University of Rio de Janeiro Rio de Janeiro RJ20550-900 Brazil COPPE/Systems Engineering Federal University of Rio de Janeiro Rio de Janeiro RJ21945-970 Brazil

ISBN: (纸本)9781479970148

In this work, we study one of the major problems in exploring the power of GPUs to accelerate video processing applications: countless frames have to be transferred back and forth between the CPU and GPU. We evaluate four different data transfer approaches currently available on modern GPUs: Standard Allocation, Pinned Memory, Data Stream, and Zero-Copy. Our results show that Data Stream is the most efficient strategy, but requires more programming effort. Zero-Copy, on the other hand, demonstrates inferior performance due to the significant latency incurred by the PCIe bus transfers for every memory access. © 2014 IEEE.

关键词： Graphics processing unit

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A GPU offloading mechanism for LHCb

A GPU offloading mechanism for LHC<i>b</i>

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20th international conference on Computing in High Energy and Nuclear Physics (CHEP)

作者： Badalov, Alexey Perez, Daniel Hugo Campora Zvyagin, Alexander Neufeld, Niko Cardona, Xavier Vilasis La Salle Ramon Llull Univ Barcelona Spain

the current computational infrastructure at LHCb is designed for sequential execution. It is possible to make use of modern multi-core machines by using multi-threaded algorithms and running multiple instances in parallel, but there is no way to make efficient use of specialized massively parallel hardware, such as graphical processing units and Intel Xeon/Phi. We extend the current infrastructure with an out-of-process computational server able to gather data from multiple instances and process them in large batches.

关键词： Graphics processing unit

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Acceleration of accurate floating point operations using SIMD 9

Acceleration of accurate floating point operations using SIM...

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9th international conference on Computer Engineering & Systems (ICCES)

作者： Abdalla, DiaaEldin M. Zaki, Ahmad M. Bahaa-Eldin, Ayman M. Ain Shams Univ Cairo Egypt

ISBN: (纸本)9781479965946

Several computing systems that use decimal number calculations suffer from the accumulation and propagation of errors. Decimal numbers are represented using specific length floating point formats and hence there will always be a truncation of extra fraction bits causing errors. Several solutions had been proposed for such a problem. Among those accurate calculation systems was the usage of vectors of floating point numbers to represent decimal values with very large accuracy, known as Multi-Number System (MN). Unfortunately, MN calculations are time consuming and are not suitable for real time applications. Several attempts for special architectures had been proposed to speed up those calculations. In this work, the Single Instruction Multiple Data (SIMD) paradigm found in modern CPUs is exploited to accelerate the MN calculations. the basic arithmetic operation algorithms had been modified to utilize the SIMD architecture and a new Square representation of operands had been proposed, this representation was introduced because the MN operations are sequential and iterative, and thus we can't apply the SIMD parallel instructions directly. the proposed architecture has an execution time that is 35 % of the original MN execution time for the division, which is the most time consuming operation while preserving the same accuracy.

关键词： floating point arithmetic parallel processing CPU MN calculations MN execution time SIMD architecture SIMD parallel instructions basic arithmetic operation algorithms computing systems decimal number calculations decimal values execution time floating point numbers floating point operations fraction-bit truncation multinumber system single-instruction multiple data paradigm specific-length floating point formats square representation Manganese floating point arithmetic SIMD architecture execution time single instruction multiple datastream manganese central processing units FLOATING POINTS parallel processing (COMPUTERS) acceleration

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Programmable Systems-on-Chip for Information processing 8

Programmable Systems-on-Chip for Information Processing

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8th IEEE international conference on Application of Information and Communication Technologies (AICT)

作者： Sklyarov, Valery Skliarova, Iouilia Univ Aveiro Dept Elect Telecommun & Informat IEETA Aveiro Portugal

ISBN: (纸本)9781479941209

Information processing is a very broad area in which many problems are computationally intensive and thus, they require parallelization and acceleration based on new technologies. the Xilinx Zynq-7000 all programmable system-on-chip can be seen as a very adequate platform permitting application-specific software and problem-targeted hardware to be coupled on a single configurable microchip. the tutorial is dedicated to multi-level software/hardware co-design techniques and system architectures that combine general-purpose computers, multi-core application-specific processing, and accelerators in reconfigurable hardware with emphasis on broad parallelism. Four projects from the scope of data processing, application informatics, parallel algorithms (mapped to hardware), and combinatorial search are briefly characterized and will be demonstrated in fully implemented and ready to test projects that include software and reconfigurable hardware linked with on-chip high-performance interfaces. Particular design examples, potential practical applications, experiments and comparisons will be demonstrated.

关键词： Information processing high-performance computing parallelism programmable systems-on-chip

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Speeding up Frequent Itemset Mining Process on XML Data using Graphic Processor 5

Speeding up Frequent Itemset Mining Process on XML Data usin...

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5th international conference on Confluence - the Next Generation Information Technology Summit (Confluence)

作者： Rathi, Sheetal Dhote, C. A. Bangera, Vivek SGBAU Amravati Maharashtra India PRMITR Badnera Maharashtra India Indian Inst Technol Bombay Maharashtra India

ISBN: (纸本)9781479942367

XML technology is being extensively used for data exchange between applications on web and hence mining these documents becomes an important area of research. Since XML is extensively used in web, efficient methods are required for knowledge discovery from the enormous collections of XML documents. Also some advanced tools and technologies are required to effectively handle this scalable data. A methodology is proposed to deal with handling such scalable XML data with the help of high performance and low cost computing, the GPU. this paper aims to parallelize the pre-processing stage of deserialization and sorting to make the dataset favorable for mining.

关键词： XML mining High performance computing Frequent Pattern mining parallel processing

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Fast GPU parallel N-Body tree traversal with Simulated Wide-Warp 20

Fast GPU parallel N-Body tree traversal with Simulated Wide-...

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20th IEEE international conference on parallel and Distributed Systems, ICPADS 2014

作者： Zola, Wagner M. Nunan Bona, Luis C.E. Silva, Fabiano Federal University of Paraná Curitiba PR Brazil

ISBN: (纸本)9781479976157

the Barnes-Hut algorithm is a widely used approximation method for the N-Body simulation problem. the irregular nature of this tree walking code presents interesting challenges for its computation on parallel systems. Additional problems arise in effectively exploiting the processing capacity of GPU architectures. We propose and investigate the applicability of software Simulated Wide-Warps (SWW) in this context. To this extent, we explicitly deal with dynamic irregular patterns in data accesses with data remapping and data transformation, by controlling execution flow divergence of threads. We present a new compact data-structure for the tree layout, GPU parallel algorithms for tree transformation and parallel walking using SWW. Benefits of our techniques are in transposing the tree algorithm to execute regular patterns to match the GPU model. Our experiments show significant performance improvement over the best known GPU solutions to this algorithm. © 2014 IEEE.

关键词： parallel algorithms

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the path toward HEP High Performance Computing

The path toward HEP High Performance Computing

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20th international conference on Computing in High Energy and Nuclear Physics (CHEP)

作者： Apostolakis, John Brun, Rene Carminati, Federico Gheata, Andrei Wenzel, Sandro European Org Nucl Res CERN Geneva Switzerland

High Energy Physics code has been known for making poor use of high performance computing architectures. Efforts in optimising HEP code on vector and RISC architectures have yield limited results and recent studies have shown that, on modern architectures, it achieves a performance between 10% and 50% of the peak one. Although several successful attempts have been made to port selected codes on GPUs, no major HEP code suite has a "High Performance" implementation. With LHC undergoing a major upgrade and a number of challenging experiments on the drawing board, HEP cannot any longer neglect the less-than-optimal performance of its code and it has to try making the best usage of the hardware. this activity is one of the foci of the SFT group at CERN, which hosts, among others, the Root and Geant4 project. the activity of the experiments is shared and coordinated via a Concurrency Forum, where the experience in optimising HEP code is presented and discussed. Another activity is the Geant-V project, centred on the development of a high-performance prototype for particle transport. Achieving a good concurrency level on the emerging parallel architectures without a complete redesign of the framework can only be done by parallelizing at event level, or with a much larger effort at track level. Apart the shareable data structures, this typically implies a multiplication factor in terms of memory consumption compared to the single threaded version, together with sub-optimal handling of event processing tails. Besides this, the low level instruction pipelining of modern processors cannot be used efficiently to speedup the program. We have implemented a framework that allows scheduling vectors of particles to an arbitrary number of computing resources in a fine grain parallel approach. the talk will review the current optimisation activities within the SFT group with a particular emphasis on the development perspectives towards a simulation framework able to profit best from t

关键词： parallel architectures

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