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Design of area and power efficient complex number multiplier 5

Design of area and power efficient complex number multiplier

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5th international conference on Computing Communication and Networking Technologies, ICCCNT 2014

作者： Premananda, B.S. Pai, Samarth S. Shashank, B. Bhat, Shashank S. Department of Telecommunication Engineering R. V. College of Engineering Bangalore560059 India

ISBN: (纸本)9781479926961

Complex number multiplication is one of the most important arithmetic operations in signal processing. the paper proposes a design of high speed 8-bit complex number multiplier where the multiplication process is carried out using Vedic Mathematics [1], Urdhva Tiryagbhyam (Vertically and Cross-wise) sutra and the addition achieved by use of modified adder architectures to reduce the area occupied and power dissipated. Multiplication is realized using modified 8-bit multipliers [2]. the proposed 8-bit multiplier [2] results in a 6.23% increase in speed, 1.88% decrease in area and 13.84% decrease in power dissipation when compared to the normal 8-bit Vedic multiplier. Further, the proposed 8-bit complex number multiplier results in a 9.11% decrease in power dissipated when compared to the normal 8-bit complex number Vedic multiplier. © 2014 IEEE.

关键词： Signal processing

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PARMA-DITAM 2014 - Proc., 5th Workshop on parallel Programming and Run-Time Manage. Tech. for Many-Core Architect. and 3rd Workshop on Design Tools and Architect. for Multicore Embedded Comput. Platforms

PARMA-DITAM 2014 - Proc., 5th Workshop on Parallel Programmi...

引用

5th Workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures and 3rd Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2014

ISBN: (纸本)9781450326070

the proceedings contain 7 papers. the topics discussed include: an interactive tool based on Polly for detection and parallelization of loops;on expressing strategies for directive-driven multicore programming models;effective platform-level exploration for heterogeneous multicores exploiting simulation-induced slacks;a cycle-accurate synthesizable MIPS simulator in Simulink;extending a run-time resource management framework to support OpenCL and heterogeneous systems;exploiting performance counters for energy efficient co-scheduling of mixed workloads on multi-core platforms;and fine-grained link locking within power and latency transaction level modelling in wormhole switching non-preemptive networks on chip.

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Resolution of Linear Algebra for the Discrete Logarithm Problem Using GPU and Multi-core architectures 1

引用

20th international Euro-Par conference on parallel processing (Euro-Par)

作者： Jeljeli, Hamza Univ Lorraine CARAMEL Project Team LORIA INRIACNRS Campus SciBP 239 F-54506 Vandoeuvre Les Nancy France

ISBN: (数字)9783319098739

ISBN: (纸本)9783319098739;9783319098722

In cryptanalysis, solving the discrete logarithm problem (DLP) is key to assessing the security of many public-key cryptosystems. the index-calculus methods, that attack the DLP in multiplicative subgroups of finite fields, require solving large sparse systems of linear equations modulo large primes. this article deals with how we can run this computation on GPU- and multi-core-based clusters, featuring InfiniBand networking. More specifically, we present the sparse linear algebra algorithms that are proposed in the literature, in particular the block Wiedemann algorithm. We discuss the parallelization of the central matrix-vector product operation from both algorithmic and practical points of view, and illustrate how our approach has contributed to the recent record-sized DLP computation in GF(2(809)).

关键词： Discrete logarithm problem sparse linear algebra parallel computing GPU acceleration multi-core processors InfiniBand

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GPU Acceleration of Finding Maximum Eigenvalue of Positive Matrices 1

引用

14th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Tian, Ning Guo, Longjiang Ai, Chunyu Ren, Meirui Li, Jinbao Heilongjiang Univ Sch Comp Sci & Technol Harbin Peoples R China Key Lab Database & Parallel Comp Heilongjiang Peoples R China Univ S Carolina Upstate Div Math & Comp Sci Upstate Peoples R China

ISBN: (数字)9783319111940

ISBN: (纸本)9783319111940;9783319111933

Matrix eigenvalue theory has become an important analysis tool in scientific computing. Sometimes, people do not need to find all eigenvalues but only the maximum eigenvalue. Existing algorithms of finding the maximum eigenvalue of matrices are implemented sequentially. With the increasing of the orders of matrices, the workload of calculation is getting heavier. therefore, traditional sequential methods are unable to meet the need of fast calculation for large matrices. this paper proposes a parallel algorithm named PA-ST to find the maximum eigenvalue of positive matrices by using similarity transformation which is implemented by CUDA (Computer Unified Device Architecture) on GPU (Graphic Process Unit). To the best of our knowledge, this is the first CUDA based parallel algorithm of calculating maximum eigenvalue of matrices. In order to improve the performance, optimization techniques are applied in this paper such as using the shared memory rather than the global memory to improve the speed of computation, avoiding bank conflicts by setting the span index, satisfying the principle of coalesced memory access, and by using single-precision floating-point arithmetic and the pinned memory to reduce the copy operation and obtain higher data transfer bandwidth between the host and the GPU device. the experimental results show that the similarity transformation technique can significantly shorten the running time compared to the sequential algorithm and the speedup ratio is nearly stable when the number of iterations increases. As the matrix order increases, the running time of the sequential algorithm and PA-ST increases correspondingly. Experiments also show that the speedup ratio of the PA-ST is between 2.85 and 35.028.

关键词： Maximum Eigenvalue Positive Matrix Similarity Transformation GPU CUDA

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Efficient concurrent processing of separable 2-D transforms in C++11 27

Efficient concurrent processing of separable 2-D transforms ...

引用

27th international conference on Computer Applications in Industry and Engineering, CAINE 2014

作者： Weiss, John M. Department of Mathematics and Computer Science South Dakota School of Mines and Technology Rapid CitySD57701-3995 United States

ISBN: (纸本)9781880843970

Separable 2-D transforms (such as the 2-D Fourier transform) are widely used in fields such as data analysis and image processing. Fast processors and divide-and-conquer algorithms have made these 2-D transforms accessible on desktop computers. Nonetheless, the widespread use of multi-core architectures makes significant efficiency improvements possible. In the past, parallel processing in C++ has been restricted to external libraries. But the recent release of C++11 introduces concurrency constructs into the language itself, providing obvious benefits to software development, optimization, and portability. this paper examines the high level concurrency interface in C++11, and demonstrates that significant efficiency gains are achievable for the 2-D Fourier transform on standard multi-core processors. this approach is readily extensible to other separable 2-D transforms such as wavelet transforms and the discrete cosine transform, and is equally applicable to other separable 2-D operations such as convolution and correlation. It promises to scale well to future multi-core processors, as additional CPUs become available. Copyright ISCA, CAINE 2014.

关键词： Efficiency

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PA*SE: parallel A* for Slow Expansions 24

PA*SE: Parallel A* for Slow Expansions

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24th international conference on Automated Planning and Scheduling (ICAPS)

作者： Phillips, Mike Likhachev, Maxim Koenig, Sven Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Southern Calif Los Angeles CA USA

ISBN: (纸本)9781577356608

Planners need to become faster as we seek to tackle increasingly complicated problems. Much of the recent improvements in computer speed is due to multi-core processors. For planners to take advantage of these types of architectures, we must adapt algorithms for parallel processing. there are a number of planning domains where state expansions are slow. One example is robot motion planning, where most of the time is devoted to collision checking. In this work, we present PA*SE, a novel, parallel version of A* (and weighted A*) which parallelizes state expansions by taking advantage of this property. While getting close to a linear speedup in the number of cores, we still preserve completeness and optimality of A* (bounded sub-optimality of weighted A*). PA*SE applies to any planning problem in which significant time is spent on generating successor states and computing transition costs. We present experimental results on a robot navigation domain (x,y,heading) which requires expensive 3D collision checking for the PR2 robot. We also provide an in-depth analysis of the algorithm's performance on a 2D navigation problem as we vary the number of cores (up to 32) as well as the time it takes to collision check successors during state expansions.

关键词： Planning

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5th international conference in Image processing and Communications, IP&C 2013

5th International Conference in Image Processing and Communi...

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5th international conference in Image processing and Communications, IP&C 2013

ISBN: (纸本)9783319016214

the proceedings contain 52 papers. the special focus in this conference is on Image processing and Communications. the topics include: Adaptive windowed threshold for box counting algorithm in cytoscreening applications;corneal endothelial grid structure factor based on coefficient of variation of the cell sides lengths;a distributed approach for development of deformable model-based segmentation methods;enhancement of low-dose CT brain scans using graph-based anisotropic interpolation;using of EM algorithm to image reconstruction problem with tomography noises;the perception of humanoid robot by human;a fast histogram estimation based on the Monte Carlo method for image binarization;adaptation of the combined image similarity index for video sequences;time-frequency analysis of image based on stockwell transform;2DKLT-based color image watermarking;knowledge transformations applied in image classification task;problems of infrared and visible-light images automatic registration;semantics driven table understanding in born-digital documents;contextual possibilistic knowledge diffusion for images classification;image feature extraction using compressive sensing;a modification of the parallel spline interpolation algorithms;local Eigen background substraction;polarization imaging in 3D shape reconstrucion;layer image components geometry optimization;extraction of data from limnigraf chart images;a simplified visual cortex model for efficient image codding and object recognition;fuzzy rule-based systems for optimizing power consumption in data centers;an algorithm for finding shortest path tree using ant colony optimization metaheuristic and a sensor network gateway for IP network and SQL database.

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parallel Implementation of the Genetic Algorithm on NVIDIA GPU Architecture for Synthesis and Inversion

Parallel Implementation of the Genetic Algorithm on NVIDIA G...

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10th international conference on Barkhausen and Micro-Magnetics (ICBM)

作者： Karthik, Victor U. Sivasuthan, Sivamayam Hoole, Samuel Ratnajeevan H. Michigan State Univ Dept Elect & Comp Engn E Lansing MI 48824 USA

ISBN: (纸本)9780735412125

the computational algorithms for device synthesis and nondestructive evaluation (NDE) are often the same. In both we have a goal a particular field configuration yielding the design performance in synthesis or to match exterior measurements in NDE. the geometry of the design or the postulated interior defect is then computed. Several optimization methods are available for this. the most efficient like conjugate gradients are very complex to program for the required derivative information the least efficient zeroth order algorithms like the genetic algorithm take much computational time but little programming effort. this paper reports launching a Genetic Algorithm kernel on thousands of compute unified device architecture (CUDA) threads exploiting the NVIDIA graphics processing unit (GPU) architecture. the efficiency of parallelization, although below that on shared memory supercomputer architectures, is quite effective in cutting down solution time into the realm of the practicable. We carry this further into multi-physics electro-heat problems where the parameters of description are in the electrical problem and the object function in the thermal problem. Indeed, this is where the derivative of the object function in the heat problem with respect to the parameters in the electrical problem is the most difficult to compute for gradient methods, and where the genetic algorithm is most easily implemented.

关键词： NDE GPU Multi-physics FEM Optimization

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Preparing HEP software for concurrency

Preparing HEP software for concurrency

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20th international conference on Computing in High Energy and Nuclear Physics (CHEP)

作者： Clemencic, M. Hegner, B. Mato, P. Piparo, D. CERN CH-1211 Geneva Switzerland

the necessity for thread-safe experiment software has recently become very evident, largely driven by the evolution of CPU architectures towards exploiting increasing levels of parallelism. For high-energy physics this represents a real paradigm shift, as concurrent programming was previously only limited to special, well-defined domains like control software or software framework internals. this paradigm shift, however, falls into the middle of the successful LHC programme and many million lines of code have already been written without the need for parallel execution in mind. In this paper we have a closer look at the offline processing applications of the LHC experiments and their readiness for the many-core era. We review how previous design choices impact the move to concurrent programming. We present our findings on transforming parts of the LHC experiment reconstruction software to thread-safe code, and the main design patterns that have emerged during the process. A plethora of parallel-programming patterns are well known outside the HEP community, but only a few have turned out to be straightforward enough to be suited for non-expert physics programmers. Finally, we propose a potential strategy for the migration of existing HEP experiment software to the many-core era.

关键词： parallel programming

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Successive Stage Multi-Round Scheduling for Cube Based Multi-Processor Systems 5

Successive Stage Multi-Round Scheduling for Cube Based Multi...

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5th IEEE international conference on Computational Intelligence and Computing Research (IEEE ICCIC)

作者： Hasan, Moin Goraya, Major Singh St Longowal Inst Engn & Technol Dept CSE Sangrur India

ISBN: (纸本)9781479939756

Multi-processor systems are advantageous in the sense that they allow concurrent execution of the given workload. the workload can be thought as the computation units which can be either processes or tasks. these processes or tasks can either be independent programs or partitioned modules of a single program. this paper presents an algorithm named as "Successive Stage Multi Round Scheduling" which is able to allocate and balance the given workload among the connected processing units of the Multi-processor system in order to improve the efficiency of the system. Simulation results are obtained using the hypercube architecture due to its simple design and high interconnectivity and results are compared with two existing schemes namely "Minimum Distance Scheduling" and "Two Round Scheduling."

关键词： cube based architectures load balancing ideal load load imbalance factor

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