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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3311 条记录，以下是1461-1470 订阅

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parallel Implementation of the Matrix Rank Test for Randomness Assessment 10

Parallel Implementation of the Matrix Rank Test for Randomne...

引用

IEEE 10th international conference on Intelligent Computer Communication and processing (ICCP)

作者： Marton, Kinga Baja, Vlad Suciu, Alin Tech Univ Cluj Napoca Dept Comp Sci Cluj Napoca Romania

ISBN: (纸本)9781479965694

the quality evaluation of random number sequences is a rather complex and resource-expensive process with a peculiar property: there is no finite amount of testing that can ensure perfect randomness. Yet applying multiple randomness tests, each evaluating the sequence from one specific and significant point of view, is vital for obtaining relevant results which can guide the tester in accepting or rejecting the considered random number sequence. therefore, aiming to satisfy the increasing demand for large volumes of high quality random data, there is a stringent need for high performance and flexible statistical tests in order to provide a more comprehensive assessment. Our work enrolls in this direction and this paper introduces the improved, extended and parallelized Matrix Rank Test (the 5th test of the NIST Statistical Test Suite), describing several enhancement methods. Experimental results prove the significant performance improvement compared to the original version and show the comparative efficiencies of the proposed parallel implementations.

关键词： statistical testing performance random number sequences matrix rank multi-core architecture efficient implementation

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Detecting a Large Number of Objects in Real-time Using Apache Storm 5

Detecting a Large Number of Objects in Real-time Using Apach...

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5th international conference on Information and Communication Technology Convergence (ICTC)

作者： Im, Dong-Hyuck Cho, Cheol-Hye Jung, IlGu ETRI Broadcasting & Telecommun Media Res Lab Daejeon South Korea

ISBN: (纸本)9781479967865

Object detection is an important function for intelligent multimedia processing, but its computational complexity prevented its pervasive uses in consumer electronics. To process large-scale datasets in real-time, more resources and reliable infrastructures are required for spreading the data and running the applications across multiple machines in parallel. In order to detect a large number of objects in real-time, a task-parallel processing framework based on Storm is proposed.

关键词： object detection parallel computing distributed computing Storm

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Agent-Based Fault-Tolerance Mechanism for Distributed Key-Value Database

Agent-Based Fault-Tolerance Mechanism for Distributed Key-Va...

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5th international conference on Digital Home (ICDH)

作者： Wu Hui-Jun Lu Kai Li Gen Jiang Jin-Fei Wang Shuang-Xi Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab Changsha Hunan Peoples R China

ISBN: (纸本)9781479942848

Distributed key-value database is widely used in Web 2.0 applications and cloud computing environments. It overcomes the weak performance and bad scalability of traditional relational database. But fault in distributed system will lead to errors, then the high performance is useless. So we should build a fault tolerance mechanism. On the other hand, in many application scenarios, transactional operations are inevitable. Some existing key-value databases utilize two-phase commit protocol or optimistic concurrency control in transaction processing. But the problems are sing-node failure and high overhead in protocol processing. Meanwhile, users' programming becomes more error-prone. this paper designs a fault tolerance and recovery mechanism on DStageDB, which is a distributed key-value database. We design an agent-based transaction processing mechanism. the transaction processing speed is improved and less user intervention is needed.

关键词： fault-tolerance key-value database agent transaction

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Low power Square and Cube architectures Using Vedic Sutras

Low power Square and Cube Architectures Using Vedic Sutras

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5th international conference on Signal and Image processing (ICSIP)

作者： Kunchigi, Vaijyanath Kulkarni, Linganagouda Kulkarni, Subhash ECE JNTU Hyberabad Andhra Pradesh India PESIT Bangalore Karnataka India

ISBN: (纸本)9780769551005

In this paper low power square and cube architectures are proposed using Vedic sutras. Low power and less area square and cube architectures uses Dwandwa yoga Duplex combination properties of Urdhva Tiryagbhyam sutra and Anurupyena sutra of Vedic mathematics. Simulation results for 8-bit square and 8-bit cube shows that proposed architectures lowers the total power consumption by 45% and area by 63% when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width. Comparison is made between conventional and Vedic method implementations of square and cube architecture. Implementation results show a significant improvement in terms of area, power and delay. Proposed square and cube arhitectures can be used for high speed and low power applications. Synthesis is done on Xilinx FPGA Device using, Xilinx Family: Spartan 3E, Speed Grade: -4. Propagation delay of the proposed 8-bit square is 4ns and area consumed in terms of slices is 22 and for 8-bit cube propogation delay is 7.72ns and area consumed in terms of slices is 58. Dynamic power estimation for square and cube are 13mW and 16mW respectively.

关键词： Vedic mathematics Dwandwa yoga Anurupyena Square Cube low power high speed

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parallel Data processing in Dynamic Hybrid Computing Environment Using MapReduce 1

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14th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Tang, Bing He, Haiwu Fedak, Gilles Hunan Univ Sci & Technol Sch Comp Sci & Engn Xiangtan 411201 Peoples R China Univ Lyon INRIA UCB Lyon 5668 UMR CNRS ENS Lyon LIP Lab Lyon France

ISBN: (数字)9783319111940

ISBN: (纸本)9783319111940;9783319111933

A novel MapReduce computation model in hybrid computing environment called HybridMR is proposed in the paper. Using this model, high performance cluster nodes and heterogeneous desktop PCs in Internet or Intranet can be integrated to form a hybrid computing environment. In this way, the computation and storage capability of large-scale desktop PCs can be fully utilized to process large-scale datasets. HybridMR relies on a hybrid distributed file system called HybridDFS, and a time-out method has been used in HybridDFS to prevent volatility of desktop PCs, and file replication mechanism is used to realize reliable storage. A new node priority-based fair scheduling (NPBFS) algorithm has been developed in HybridMR to achieve both data storage balance and job assignment balance by assigning each node a priority through quantifying CPU speed, memory size and I/O bandwidth. Performance evaluation results show that the proposed hybrid computation model not only achieves reliable MapReduce computation, reduces task response time and improves the performance of MapReduce, but also reduces the computation cost and achieves a greener computing mode.

关键词： Hybrid Computing Environment Distributed File System MapReduce Volunteer Computing Fault-tolerance

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Methodologies and Application of Machine Learning algorithms to Classify the Performance of High Performance Cluster Components 16

Methodologies and Application of Machine Learning Algorithms...

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16th IEEE international conference on Cluster Computing (CLUSTER)

作者： Romero, Phil Idler, Craig Los Alamos Natl Lab High Performance Comp 1 Los Alamos NM 87545 USA Los Alamos Natl Lab High Performance Comp 5 Los Alamos NM USA

ISBN: (纸本)9781479955480

High Performance Computing Clusters are designed to host highly parallelized applications, often in excess of thousands of nodes allocated to a job. these jobs, especially those that require a high level of synchronous communication, can be greatly affected by a single poor, or even sub-standard performing component. these components, often referred to as a node, are typically comprised of CPUs, accelerator processors, memory, a communication bus, and so on. Consequently it is important to identify and eliminate these sub-standard performing nodes before a job is scheduled onto them. In this paper we will describe the process used to measure and the methodology used to quantify poor performing nodes or classify suspect performing nodes into groups, or clusters, that can be later used to identify future performance issues. this process is more involved than simply running a scientific calculation across all the nodes, finding one that was "slow", and labeling it as a bad node. At Los Alamos, this methodology has been used successfully to find problem nodes and has helped characterize the components of other clusters to aid in the proactive elimination of potential problems.

关键词： learning (artificial intelligence) parallel processing performance evaluation CPU accelerator processors high performance computing clusters parallelized applications poor performing nodes scientific calculation suspect performing nodes synchronous communication Bandwidth Clustering algorithms Graphics processing units Principal component analysis Standards Testing synchronous communication Clustering algorithms central processing units parallel processing (COMPUTERS) Ganglia Bandwidth Performance Evaluation Machine learning algorithms principal components analysis Graphics processing Unit jobs MACHINE APPLICATIONS

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Efficient multi-kernel ray tracing for GPUs

Efficient multi-kernel ray tracing for GPUs

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9th international conference on Computer Graphics theory and Applications, GRAPP 2014

作者： Schiffer, thomas Fellner, Dieter W. Institut für ComputerGraphik and Wissensvisualisierung Technische Universität Graz Graz Austria Graphisch-Interaktive Systeme Technische Universität Darmstadt Darmstadt Germany Fraunhofer Institut für Graphische Datenverarbeitung Fraunhofer Gesellschaft Darmstadt Germany

ISBN: (纸本)9789897580024

Images with high visual quality are often generated by a ray tracing algorithm. Despite its conceptual simplicity, designing an efficient mapping of ray tracing computations to massively parallel hardware architectures is a challenging *** this paper we investigate the performance of state-of-the-art ray traversal algorithms for bounding volume hierarchies on GPUs and discuss their potentials and limitations. Based on this analysis, a novel ray traversal scheme called batch tracing is proposed. It decomposes the task into multiple kernels, each of which is designed for efficient parallel execution. Our algorithm achieves comparable performance to currently prevailing approaches and represents a promising avenue for future research.

关键词： Graphics processing unit

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Design of area and power efficient complex number multiplier 5

Design of area and power efficient complex number multiplier

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5th international conference on Computing Communication and Networking Technologies, ICCCNT 2014

作者： Premananda, B.S. Pai, Samarth S. Shashank, B. Bhat, Shashank S. Department of Telecommunication Engineering R. V. College of Engineering Bangalore560059 India

ISBN: (纸本)9781479926961

Complex number multiplication is one of the most important arithmetic operations in signal processing. the paper proposes a design of high speed 8-bit complex number multiplier where the multiplication process is carried out using Vedic Mathematics [1], Urdhva Tiryagbhyam (Vertically and Cross-wise) sutra and the addition achieved by use of modified adder architectures to reduce the area occupied and power dissipated. Multiplication is realized using modified 8-bit multipliers [2]. the proposed 8-bit multiplier [2] results in a 6.23% increase in speed, 1.88% decrease in area and 13.84% decrease in power dissipation when compared to the normal 8-bit Vedic multiplier. Further, the proposed 8-bit complex number multiplier results in a 9.11% decrease in power dissipated when compared to the normal 8-bit complex number Vedic multiplier. © 2014 IEEE.

关键词： Signal processing

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Resolution of Linear Algebra for the Discrete Logarithm Problem Using GPU and Multi-core architectures 1

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20th international Euro-Par conference on parallel processing (Euro-Par)

作者： Jeljeli, Hamza Univ Lorraine CARAMEL Project Team LORIA INRIACNRS Campus SciBP 239 F-54506 Vandoeuvre Les Nancy France

ISBN: (数字)9783319098739

ISBN: (纸本)9783319098739;9783319098722

In cryptanalysis, solving the discrete logarithm problem (DLP) is key to assessing the security of many public-key cryptosystems. the index-calculus methods, that attack the DLP in multiplicative subgroups of finite fields, require solving large sparse systems of linear equations modulo large primes. this article deals with how we can run this computation on GPU- and multi-core-based clusters, featuring InfiniBand networking. More specifically, we present the sparse linear algebra algorithms that are proposed in the literature, in particular the block Wiedemann algorithm. We discuss the parallelization of the central matrix-vector product operation from both algorithmic and practical points of view, and illustrate how our approach has contributed to the recent record-sized DLP computation in GF(2(809)).

关键词： Discrete logarithm problem sparse linear algebra parallel computing GPU acceleration multi-core processors InfiniBand

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PARMA-DITAM 2014 - Proc., 5th Workshop on parallel Programming and Run-Time Manage. Tech. for Many-Core Architect. and 3rd Workshop on Design Tools and Architect. for Multicore Embedded Comput. Platforms

PARMA-DITAM 2014 - Proc., 5th Workshop on Parallel Programmi...

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5th Workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures and 3rd Workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2014

ISBN: (纸本)9781450326070

the proceedings contain 7 papers. the topics discussed include: an interactive tool based on Polly for detection and parallelization of loops;on expressing strategies for directive-driven multicore programming models;effective platform-level exploration for heterogeneous multicores exploiting simulation-induced slacks;a cycle-accurate synthesizable MIPS simulator in Simulink;extending a run-time resource management framework to support OpenCL and heterogeneous systems;exploiting performance counters for energy efficient co-scheduling of mixed workloads on multi-core platforms;and fine-grained link locking within power and latency transaction level modelling in wormhole switching non-preemptive networks on chip.

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