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A Comparison Between CPU and GPU Computing in DNN-Based DoA Estimation

A Comparison Between CPU and GPU Computing in DNN-Based DoA ...

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UNIfied conference of international Workshop on Defence Applications of Multi-Agent Systems, DAMAS 2023, international conference on Maintenance Engineering, IncoME-V 2023, international conference on the Efficiency and Performance Engineering Network, TEPEN 2023

作者： Kokkinis, Georgios Ahmed, Qasim Z. Sambell, Alistair Chochliouros, Ioannis P. Lazaridis, Pavlos I. Zaharis, Zaharias D. School of Computing and Engineering University of Huddersfield HuddersfieldHD1 3DH United Kingdom Marousi151 24 Greece School of Electrical and Computer Engineering Aristotle University of Thessaloniki Thessaloniki Greece

ISBN: (纸本)9783031494208

Deep Learning algorithms have recently become accessible to modern Telecommunication systems due to the advancement in both hardware and software technology. the massively parallel computational tasks of Artificial Intelligence (AI) training are now directly performed in Graphic processing Units (GPUs), which contain many processing cores. this paper tests the improvement in computing time for Deep Neural Network (DNN) architectures that solve the Direction of Arrival (DoA) estimation problem as a classification task by utilizing the Nvidia CUDA framework. the training and testing data are generated by receiving signal information from a simulated antenna array. the input of the DNN is a 64 × 64 image with two channels, whereas the problem is modelled as a multi-label classification task. the purpose of this research is to observe the acceleration that the GPU provides in the DoA estimation classification problem. the project includes benchmarks from a wide range of computing systems and the results demonstrate the potential of DNN-based DoA estimators as a modern technology that can be deployed on available commercial hardware. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2024.

关键词： Graphics processing unit

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Smart Aquarium Caring System Using Image processing and IoT 5

Smart Aquarium Caring System Using Image Processing and IoT

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5th international conference on Advancements in Computing, ICAC 2023

作者： Jayasinghe, Maheshi Wettewa, Awasha Senanayake, Bhagya Dasanayake, Sashintha Chandrasiri, Sanjeevi Kumari, Suriyaa Sri Lanka Institute of Information Technology Department of Information Technology Malabe Sri Lanka

ISBN: (纸本)9798350358131

the expansion of the ornamental fish sector significantly contributes to Sri Lanka's economy. Nevertheless, manual practices within aquariums pose various limitations, impeding further growth. Manual methods for disease identification and growth detection heavily rely on expertise, while water quality monitoring practices are complex and costly. Accordingly, this research proposes a hybrid approach using image processing and IoT to automate the crucial aspects of aquarium care, including disease detection, water quality monitoring, and growth prediction. During disease detection, three different CNN architectures' performances were compared, and ResNet50 achieved the highest accuracy of 99.21%. the classifier identifies three types of fish diseases, including Redspot, Whitespot, and Tailrot. Water quality is monitored by measuring the pH, turbidity, and temperature levels in a tank using sensors in real time. the ESP32 microcontroller was used as the connector, and the Arduino IDE was utilized for the programming. Due to cost-effectiveness, the dissolved oxygen amount is predicted by the Random Forest Regressor with an R-squared of 0.83. Additionally, fish growth detection is performed to identify different growth stages of 1-6-month-old goldfish, and the ResNet50 achieved 85.5% accuracy. By integrating all three aspects, the proposed approach aims to provide a comprehensive and cost-effective solution for aquarium care. © 2023 IEEE.

关键词： Dissolved oxygen

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SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems 51

SPAMeR: Speculative Push for Anticipated Message Requests in...

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51st international conference on parallel processing (ICPP)

作者： Wu, Qinzhe Ekanayake, Ashen Li, Ruihao Beard, Jonathan John, Lizy K. Univ Texas Austin Austin TX 78712 USA Arm Inc Austin TX USA

ISBN: (纸本)9781450397339

With increasing core counts and multiple levels of cache memories, scaling multi-threaded and task-level parallel workloads is continuously becoming a challenge. A key challenge to scaling the number of communicating tasks (or threads) is the rate at which existing communication mechanisms scale (in terms of latency and bandwidth). architectures with hardware accelerated queuing operations have the potential to reduce the latency and improve scalability of moving data between processing elements, reducing synchronization penalties, and thereby improving the performance of task-level parallel workloads. While hardware queues reduce synchronization penalties, they cannot fully hide load-to-use latency, i.e., perfect pipelines often are not realized. there is the potential, however, for better overlap. If the inter-processor communication latency is equal to or less than the time spent processing a message at the consumer, any and all latency may be overlapped while the consumer is processing. We exploit this property to speedup parallel applications above and beyond existing hardware queues. In this paper, we present SPAMeR, a speculation mechanism built on top of a state-of-the-art hardware-driven message queue architecture. SPAMeR has the capability to speculatively push messages in anticipation of consumer message requests. Unlike pre-fetch approaches which predict what addresses to fetch next, with a queue we know exactly what data is needed next but not when it is needed;SPAMeR adds algorithms that attempt to predict this. We evaluate the effectiveness of SPAMeR with a set of diverse task-parallel benchmarks utilizing the gem5 full system simulator, and observe a 1.33x average speedup.

关键词： multi-core system parallel computing message queue speculation

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Novel Scheduling and Shifter Networks for 5G LDPC Decoders 18th

Novel Scheduling and Shifter Networks for 5G LDPC Decoders

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18th international Workshop on Design and Architecture for Signal and Image processing, DASIP 2025

作者： Papageorgiou, Nikos Paliouras, Vassilis Department of Electrical and Computer Engineering University of Patras Patras Greece

ISBN: (纸本)9783031878961

Low Density Parity Check (LDPC) codes under iterative decoding have shown remarkable error correction capabilities, with moderate complexity requirements. Initially, in this paper a check based on a part of the parity check matrix (core part check) is presented. the proposed check is amenable for hardware implementation and allows the termination of the decoding procedure at a sub-iteration level, i.e., within an iteration. In this way the number of clock cycles required reduced by 150 for the semi-parallel architecture and for 5G NR codes. Simultaneously the Block Error Rate (BLER) remains the same while hardware becomes simpler. In addition, this paper introduces a novel scheduling scheme combined with the core part check and a syndrome-select logic. Experimental results are offered, assuming the parallel architecture, which show that the proposed rescheduling reduces the average number of required clock cycles per decoded word. Simultaneously improves the BLER utilizing exactly the same hardware. Specifically, targeting 5G NR LDPC codes, gains of 35% are achieved, for both the OMS and NMS algorithms. Furthermore, an innovative approach for the merge network of the reconfigurable barrel shifter is proposed. Finally, an ASIC implementation for semi-parallel architecture and the energy consumption gained with the proposed algorithm are presented. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： parallel architectures

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Relative Gradient Matching Cost for Mitigating Feature Discrepancies in Stereo Matching 5

Relative Gradient Matching Cost for Mitigating Feature Discr...

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5th international conference on High Performance Big Data and Intelligent Systems, HDIS 2023

作者： Liu, Changlin Zhang, Yuan Sun, Linjun Zhang, Kaijie Cao, Bing Li, Zhiwei School of Semiconductor Science and Technology South China Normal University Guangzhou China School of Information Science and Technology Beijing Forestry University Beijing China AnnLab Institute of Semiconductors Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350394160

In stereo matching, perspective differences in images can cause feature inconsistencies. Traditional stereo matching algorithms compare pixel disparities using local parallel windows transformed by matching costs. However, this method under the fronto-parallel windows assumption may produce incorrect matching results when there are perspective differences in the feature scale. To address this issue, we propose a new cost computation method called relative gradient matching cost (RGC). RGC effectively handles feature perspective differences by robustly constraining feature matching relationships across varying object surface depths, simulating the effect of slanted support windows. We propose different improvement strategies for common traditional methods and DNN-based methods combined with RGC. In experiments, we compare the performance of RGC with some SOTA models. the experiment results demonstrate that RGC significantly improves the accuracy and stability of stereo matching, especially in cases with edge and discontinuity areas. ©2023 IEEE.

关键词： Stereo image processing

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Research on Infrared Pixel Coupled Polarization Image Acquisition and processing System Based on Self made Circuit and IP Core 5

Research on Infrared Pixel Coupled Polarization Image Acquis...

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5th international conference on Optoelectronic Science and Materials, ICOSM 2023

作者： Cui, Beiyao Wang, Feng Li, Qinghui Jia, Rong Department of Information Engineering PLA Army Academy of Artillery and Air Defense Hefei China

ISBN: (纸本)9781510674547

the lack of integrated acquisition and processing circuits in pixel coupled infrared polarization cameras restricts the development and application of polarization technology. FPGA has the ability of parallel processing, which can meet the needs of simultaneous transmission and processing of multi-channel data, with high data throughput and fast processing speed. At the same time, there are a large number and diverse types of IO ports that can be combined with different interface chips to design multiple types of interface circuits and achieve various circuit functions. therefore, based on the FPGA core chip, this article designs peripheral acquisition, transmission, storage, and display circuits to complete the image acquisition and display of pixel coupled polarization cameras. During the circuit design process, the concept of modular design is adopted, and the schematic diagram of the module circuit is designed according to functional requirements. Based on the schematic diagram, a PCB is drawn, and the final product circuit board is produced. Based on the IP core and HLS library, the acquisition and processing software program was designed, and polarization image acquisition and polarization information calculation were completed. Finally, an experimental verification was conducted on the functionality of the circuit system using the idea of modularization first and then overall verification. through verification, the circuit system can meet the functions of pixel coupled infrared polarization camera image acquisition, processing, and display. © 2024 SPIE.

关键词： Pixels

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HPC Driven Innovations in Network Management for Greater Efficiency and Productivity 5

HPC Driven Innovations in Network Management for Greater Eff...

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5th international conference on Inventive Research in Computing Applications, ICIRCA 2023

作者： Veerla, Harsha Chindukuri, Vinay Mohammed, Yaseen Junaid Palakonda, Vinay Chintala, Radhika Rani Koneru Lakshmaiah Education Foundation Computer Science and Engineering A.P Vaddeswaram India

ISBN: (纸本)9798350321425

High Performance Computing (HPC) is generally a powerful computing system and software which is used to solve complex computational problems that the today's computing methods fail to solve. HPC systems use parallel processing methods, distributed computing, and specialized hardware like FPGA (Field programmable gate arrays) and GPU (Graphics processing unit) to get high level of performance. Developing of HPC systems has become rapidly evolving field, to bring out the new technologies of hardware and software for optimization techniques and managing to get better performance. HPC systems are used in wide range of machine learning, scientific and engineering applications including weather forecasting etc. Users can also use HPC to run complex modelling problems such as nuclear physics, AI (Artificial Intelligence), climate modelling etc. It is applied to solve transaction processing, data ware houses like business uses. It will perform high number of operations in no time and completes the operations under a tight deadline. In this computing method user can solve many computational things parallelly. It is also known as Supercomputing which performs operations at highest rate on computers which can perform more than a quadrillion floating-point calculations per second. In this article the present and emerging application domains of HPC and the role of it in shaping the future of networking are addressed. © 2023 IEEE.

关键词： Graphics processing unit

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Dynamic Privacy Protection with Large Language Model in Social Networks 24th

Dynamic Privacy Protection with Large Language Model in So...

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24th international conference on algorithms and architectures for parallel processing, ICA3PP 2024

作者： Xie, Yizhe Zhu, Congcong Zhang, Xinyue Hu, Xiangyu Liu, Xuan School of Data Science City University of Macau Macau China Hainan International College Minzu University of China Hainan China School of Information Engineering Minzu University of China Beijing China School of Information and Software Engineering University of Electronic Science and Technology of China Sichuan China

ISBN: (纸本)9789819615445

In contemporary social networks, dynamic privacy protection remains a pivotal yet challenging endeavor due to the intricate and evolving nature of information exchange. Traditional privacy models, predominantly static, falter in effectively safeguarding privacy amidst the complex interplay of continuously changing network interactions and structures. Addressing these deficiencies, this study introduces a novel dynamic privacy protection system anchored by large language model (LLM). Leveraging the natural language processing prowess of LLM, this system excels in real-time, context-sensitive analysis and protection of textual data within vast and variable social networks. By integrating closed-loop control theory, the system adeptly balances robust privacy safeguards with the requisite fluidity of information exchange. Experimental validations on large network datasets illustrate the system’s adeptness in balancing privacy leaks and information distortion through intelligent adaptations to privacy thresholds and strategic noise injection. the outcomes highlight the system’s utility in enhancing data security and operational efficiency, promising significant implications for future applications in broader domains such as mobile computing and IoT. this study not only propels forward the capabilities of dynamic privacy protection mechanisms but also sets a foundational architecture for subsequent innovations in privacy-sensitive, data-intensive environments. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Differential privacy

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A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image processing 4

A High-Speed Computational Pipeline Single MAC-Based VLSI Ar...

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4th international conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, ICAECT 2024

作者： Vaithiyanathan, Dhandapani James, Britto Pari Mariammal, Karuthapandian National Institute of Technology Delhi Delhi110036 India Vel Tech Rangarajan Dr. Sagunthala R and D Institute of Science and Technology Chennai600062 India Anna University Madras Institute of Technology Chennai600044 India

ISBN: (纸本)9798350343670

VLSI architectures play a vital role in most real-time applications because of their optimal performance. In this work, a single MAC (Multiply-Accumulate) based pipelined architecture is proposed for faster computation of the one-dimension (1-D) discrete wavelet transform (DWT). the main objective of this work is to reduce computational complexity by utilizing resource sharing and to enhance the speed of operation by employing a pipelining scheme. the designed single MAC-based architecture for computing DWT is suitable for infrasound data processing which employs a high-pass filter (HPF) and low-pass filter (LPF). the architecture efficiently implements a resource-sharing scheme by adopting only these two filters. In addition, in this realization, pipelining is utilized to achieve high-speed computation of DWT. Further, this design makes use of common elements several times which provide a convenient and suitable implementation. the proposed structure is coded using Verilog and implemented in FPGA (Field Programmable Gate Array) hardware with the Xilinx platform. Intending easily transported and real-time utilization, this architecture is realized using Xilinx Virtex-5 series FPGA. the area of the proposed architecture is reduced by about 44.8% when examining conventional parallel MAC architecture. Likewise, this pipelined design offers power conservation of about 31.97% over the parallel design. Further, the proposed architecture offers an operating speed of 276MHz with a power conservation of 200mW at 276MHz clock frequency. © 2024 IEEE.

关键词： DWT FPGA Device High-Speed Low-Power MAC Pipelining VLSI Architecture

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GPU parallelization and Optimization of a Combustion Simulation Application 24

GPU Parallelization and Optimization of a Combustion Simulat...

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24th IEEE international conference on High Performance Computing and Communications, 8th IEEE international conference on Data Science and Systems, 20th IEEE international conference on Smart City and 8th IEEE international conference on Dependability in Sensor, Cloud and Big Data Systems and Application, HPCC/DSS/SmartCity/DependSys 2022

作者： Liao, Zhixiang Liu, Yongzhou Che, Yonggang Institute for Quantum Information College of Computer National University of Defense Technology State Key Laboratory of High Performance Computing Changsha China

ISBN: (纸本)9798350319934

Graphics processing units (GPUs) are widely used in the area of scientific computing. While GPUs provide much higher peak performance, efficient implementation of real applications on the GPU architectures is still a non-trivial task. It is crucial to realize efficient solution algorithms that can better utilize GPU architectures. this paper presents our efforts in parallelizing and optimizing LESAP, a CFD application for scramjet combustion simulation, on NVIDIA GPUs. the GPU parallelization is realized based on the CUDA programming model, with a data-parallel implicit time-marching method that is efficient on the GPU architecture. Furthermore, shared memory and redundant calculation are proposed to reduce memory access overhead during GPU computation, and data transfer between CPU and GPU is optimized by packing the data to be transferred. the experimental results show that the GPU version, when runs on four V100 GPUs, achieves a speedup of 11.26 times compared to the CPU version that runs on two 24-core Intel Skylake Gold 6240R CPUs. Excellent parallel scalability across multiple GPUs is also observed. © 2022 IEEE.

关键词： Graphics processing unit

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