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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3293 条记录，以下是1521-1530 订阅

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parallel K-Medoids Clustering Algorithm Based on Hadoop

Parallel K-Medoids Clustering Algorithm Based on Hadoop

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2014 IEEE 5th international conference on Software Engineering and Service Science

作者： Yaobin Jiang Jiongmin Zhang Department of Computer Science and Technology East China Normal UniversityECNU

the K-Medoids clustering algorithm solves the problem of the K-Means algorithm on processing the outlier samples,but it is not be able to process big-data because of the time complexity[1].MapReduce is a parallel programming model for processing big-data,and has been implemented in *** order to break the big-data limits,the parallel KMedoids algorithm HK-Medoids based on Hadoop was *** submitted job has many iterative MapReduce procedures: In the map phase,each sample was assigned to one cluster whose center is the most similar with the sample;in the combine phase,an intermediate center for each cluster was calculated;and in the reduce phase,the new center was *** iterator stops when the new center is similar to the old *** experimental results showed that HK-Medoids algorithm has a good clustering result and linear speedup for big-data.

关键词： Clustering Analysis K-Medoids Map Reduce Hadoop Big-Data

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Novel Multi-Layer Network Decomposition Boosting Acceleration of Multi-core algorithms

Novel Multi-Layer Network Decomposition Boosting Acceleratio...

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IEEE 24th international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Grivas, Athanasios K. Mak, Terrence Yakovlev, Alex Wray, Jonny Newcastle Univ Sch Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781479904945;9781479904938

Complex networks are a technique for the modeling and analysis of large data sets in many scientific and engineering disciplines. Due to their excessive size conventional algorithms and single core processors struggle with the efficient processing of such networks. Employing multi-core graphic processing units (GPUs) could provide sufficient processing power for the analysis of such networks. However, commonly designed algorithms cannot exploit these massively parallel processing power for the analysis of such networks. In this paper, we present the Multi Layer Network Decomposition (MLND) approach which provides a general approach for parallel network analysis using multi-core processors via efficient partitioning and mapping of networks onto GPU architectures. Evaluation using a 336 core GPU graphic card demonstrated a 16x speed-up in complex network analysis relative to a CPU based approach.

关键词： graphics processing units multiprocessing systems parallel processing

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Replication-Based Fault-Tolerance for Large-Scale Graph processing

Replication-Based Fault-Tolerance for Large-Scale Graph Proc...

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international conference on Dependable Systems and Networks (DSN)

作者： Peng Wang Kaiyuan Zhang Rong Chen Haibo Chen Haibing Guan Shanghai Key Laboratory of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University Department of Computer Science Shanghai Jiao Tong University

the increasing algorithm complexity and dataset sizes necessitate the use of networked machines for many graph-parallel algorithms, which also makes fault tolerance a must due to the increasing scale of machines. Unfortunately, existing large-scale graph-parallel systems usually adopt a distributed checkpoint mechanism for fault tolerance, which incurs not only notable performance overhead but also lengthy recovery time. this paper observes that the vertex replicas created for distributed graph computation can be naturally extended for fast in-memory recovery of graph states. this paper proposes Imitator, a new fault tolerance mechanism, that supports cheaply maintenance of vertex states by replicating vertex states to their replicas during normal message exchanges, and provides fast in-memory reconstruction of failed vertices from replicas in other machines. Imitator has been implemented by extending Hama, a popular open-source clone of Pregel. Evaluation shows that Imitator incurs negligible performance overhead (less than 5% for all cases) and can recover from failures of more than one million of vertices with less than 3.4 seconds.

关键词： Fault tolerance Fault tolerant systems Computer crashes Checkpointing Synchronization Clustering algorithms Computational modeling

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Efficient Non-uniform Channelization for SDR Using Frequency Domain Filtering

Efficient Non-uniform Channelization for SDR Using Frequency...

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2014 IEEE 5th international conference on Software Engineering and Service Science

作者： Tian-li Jiang Ke-xian Gong Hua Peng Di Wu Institute of Information Systems Engineering Information Engineering University

An arbitrary sampling rate conversion algorithm based on frequency domain filtering(FDF-ASRC) is *** number of Fourier coefficients in FDF-ASRC is irrelevant to the symbol rate of interested *** the resampling algorithm to non-uniform channelization,a few modules of Fourier transform(FT) and inverse Fourier transform(IFT) can guarantee infinite channels in ***,the sampling rate of output signal can be adjusted to an integer multiple of symbol rate,which can be passed to demodulator *** comparison with seven architectures of non-uniform channelizers,the computational complexity of the proposed channelizers is equal to the best.

关键词： SD Non-uniform channelization Multi-rate signal processing Arbitrary sampling rate conversion Frequency domain filtering

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Peak Power Management for scheduling real-time tasks on heterogeneous many-core systems

Peak Power Management for scheduling real-time tasks on hete...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Waqaas Munawar Heba Khdr Santiago Pagani Muhammad Shafique Jian-Jia Chen Jörg Henkel Karlsruhe Institute of Technology (KIT) Germany Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE

the number and diversity of cores in on-chip systems is increasing rapidly. However, due to the thermal Design Power (TDP) constraint, it is not possible to continuously operate all cores at the same time. Exceeding the TDP constraint may activate the Dynamic thermal Management (DTM) to ensure thermal stability. Such hardware based closed-loop safeguards pose a big challenge in using many-core chips for real-time tasks. Managing the worst-case peak power usage of a chip can help toward resolving this issue. We present a scheme to minimize the peak power usage for frame-based and periodic real-time tasks on many-core processors by scheduling the sleep cycles for each active core and introduce the concept of a sufficient test for peak power consumption for task feasibility. We consider both inter-task and inter-core diversity in terms of power usage and present computationally efficient algorithms for peak power minimization for these cases, i.e., a special case of “homogeneous tasks on homogeneous cores” to the general case of “heterogeneous tasks on heterogeneous cores”. We evaluate our solution through extensive simulations using the 48-core SCC platform and gem5 architecture simulator. Our simulation results show the efficacy of our scheme.

关键词： Power demand Schedules Real-time systems Multicore processing Minimization Partitioning algorithms thermal management

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LTE physical layer implementation based on GPP multi-core parallel processing and USRP platform

LTE physical layer implementation based on GPP multi-core pa...

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international conference on Communications and Networking in China (CHINACOM)

作者： Zhiping Chen Jun Wu College of Electronics and Information Engineering Tongji University Shanghai China

ISBN: (纸本)9781479959716

Software defined radio (SDR) is characterized by its flexibility and convenience of modification, because significant amounts of signal processing are handed over to the general-purpose processor (GPP), rather than being done in special-purpose hardware. In the long term, software-defined radios work well in low data transmission rate systems such as 2G/3G cellular systems and other wireless radio systems. With rapid development of GPP power, more complex algorithms and higher data rate wireless communication systems can be implemented with GPP processor and general purpose RF front end. In this paper we propose a LTE physical layer parallel system architecture based on multicore GPP to match up the high capacity requests of LTE air interface. Firstly, we analyzed the complexity of each LTE physical layer module and made a statistics of their processing time. And then we used Linux CPU affinity to allocate each LTE module to particular CPU core carefully based on the statistics. CPU utilization rate shows that using multi-core makes the system to have enough capacity. Our system can only match up 2M bandwidth when the LTE physical layer procedures are running on single CPU core, while it can match up 5M bandwidth when it's running on multi-core.

关键词： Uplink Downlink Decoding Multicore processing Bandwidth Physical layer Instruction sets

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A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs

A Locality-Preserving Write Buffer Design for Page-Mapping M...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Sheng Min Huang Li Pin Chang Department of Computer Science National Chiao-Tung University Taiwan

ISBN: (纸本)9781479961245

Advanced SSDs employ a RAM-based write buffer to improve their write performance. the buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. this work presents a novel buffer algorithm for page-mapping multichannel SSDs. We propose grouping temporally or spatially correlated buffer pages and writing these grouped buffer pages to the same flash block. this strategy dramatically increases the probability of bulk data invalidations in flash blocks. In multichannel architectures, channels are assigned to their own groups of buffer pages for writing, and so channel striping does not divide a group of correlated buffer pages into small pieces. We have conducted simulations and experiments using a SSD simulator and a real SSD platform, respectively. Our results show that our design greatly outperforms existing buffer algorithms.

关键词： Ash Writing Buffer storage Algorithm design and analysis parallel processing Heuristic algorithms Correlation

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A multicore-aware von Neumann programming model

A multicore-aware von Neumann programming model

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international conference on Software Engineering and Applications (ICSOFT-EA)

作者： János Végh Zsolt Bagoly Ádám Kicsák Péter Molnár Faculty of Informatics University of Debrecen Debrecen Hungary PhD School of Informatics University of Debrecen Debrecen Hungary

An extension to the classic von Neumann paradigms is suggested, which -from the point of view of chip designers- considers modern many-core processors, and -from the point of view of programmers- still remains the classic von Neumann programming model. the work is based on the ideas that 1) the order in which the instructions (and/or code blocks) are executed does not matter, if some constraints do not force a special order of execution 2) a High Level parallelism for code blocks (similar to Instruction Level parallelism for instructions) can be introduced, allowing high-level out of order execution 3) discovering the possibilities for out of order execution can be done during compile time rather than runtime 4) the optimization possibilities discovered by the compile toolchain can be communicated to the processor in form of meta-information 5) the many computing resources (cores) can be assigned dynamically to machine instructions. It is shown that the multicore architectures could be transformed to a strongly enhanced single core processor. the key blocks of the proposal are a toolchain preparing the program code to run on many cores, a dispatch unit within the processor making effective use of the parallelized code, and also a much smarter communication method between the two key blocks is needed.

关键词： Computational modeling Multicore processing Hardware parallel processing Out of order Programming

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Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

引用

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

the desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. these systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. this new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

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A parallel data preprocessing algorithm for hierarchical clustering

A Parallel data preprocessing algorithm for hierarchical clu...

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5th international conference on Measuring Technology and Mechatronics Automation (ICMTMA)

作者： Li Zhao-Peng Li Zhao-jian Hunan Univ Humanities Sci & Technol Loudi 417000 Peoples R China

ISBN: (纸本)9780769549323;9781467356527

Hierarchical clustering technology plays a very important role in image processing, intrusion detection and bioinformatics applications, which is one of the most extensively studied branch in data mining. Presently the parallel hierarchical algorithms aren't very good at processing large data. To overcome this shortcomings, a new parallel data preprocessing algorithm based on Hierarchical Clustering is proposed in this paper this algorithm can reduce the scale of data and runtime. accounting for one tenth of it in the best situation. the experiment proof the performance of our algorithm.

关键词： hierarchical clustering parallel algorithms data preprocessing

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