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Efficient Hardware Calculation of Running Statistics

Efficient Hardware Calculation of Running Statistics

引用

28th international conference on Image and Vision Computing New Zealand (IVCNZ)

作者： Bailey, Donald G. Klaiber, Michael J. Massey Univ Sch Engn & Adv Technol Palmerston North New Zealand Univ Stuttgart Inst Parallel & Distributed Syst Stuttgart Germany

ISBN: (纸本)9781479908837;9781479908820

Calculation of mean, variance and standard deviation are often required for segmentation or feature extraction. In image processing, often an integer approximation is adequate. Conventional methods require division and square root operations, which are expensive to realize in hardware in terms of both the amount of required resources and latency. A new class of iterative algorithms is developed based on integer arithmetic. An implementation of the algorithms as a hardware architecture for a Field-Programmable Gate Array (FPGA) is compared with architectures using the conventional approach, which shows a significantly reduced latency while using less hardware resources.

关键词： Computer hardware hardware resource Field programmable gate arrays hardware architecture Iterative algorithms Feature extraction ARCHITECTURE Integer Latency integer arithmetic segmentation

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Implementation of CUDA GPU-Based parallel Computing on Smith-Waterman Algorithm to Sequence Database Searches

Implementation of CUDA GPU-Based Parallel Computing on Smith...

引用

5th international conference on Advanced Computer Science and Information Systems (ICACSIS)

作者： Bustamam, Alhadi Ardaneswari, Gianinna Lestari, Dian Univ Indonesia Dept Math Depok Indonesia

ISBN: (纸本)9789791421195

In bioinformatics, one of the gold-standard algorithms to compute the optimal similarity score between sequences in a sequence database searches is Smith-Waterman algorithm that uses dynamic programming. this algorithm has a quadratic time complexity which requires a long computation time for large-sized data. In this issue, parallel computing is essential for sequence database searches in order to reduce the running time and to increase the performance. In this paper, we discuss the parallel implementation of Smith-Waterman algorithm in GPU using CUDA C programming language with NVCC compiler on Linux environment. Furthermore, we run the performance analysis using three parallelization models, including Inter-task parallelization, Intra-task parallelization, and a combination of both models. Based on the simulation results, a combination of both models has better performance than the others. In addition the parallelization using combination of both models achieves an average speed-up of 313X and an average efficiency with a factor of 0.93.

关键词： sequential data base parallel processing (COMPUTERS) parallelization complexity classes computational time Database searching Runtime

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Enhancing the Performance of a Microarray Gridding Algorithm via GPU Computing Techniques

Enhancing the Performance of a Microarray Gridding Algorithm...

引用

IEEE 13th international conference on Bioinformatics and Bioengineering (BIBE)

作者： Katsigiannis, Stamos Zacharia, Eleni Maroulis, Dimitris Univ Athens Real Time Syst & Image Anal Lab Dept Informat & Telecommun Athens 15703 Greece

ISBN: (纸本)9781479931637

cDNA microarrays are a useful tool for studying the expression levels of genes. Nevertheless, microarray image gridding remains a challenging and complex task. Most of the microarray image analysis tools require human intervention, leading to variations of the gene expression results. Automatic methods have also been proposed, but present high computational complexity. In this work, the performance enhancement via GPU computing techniques of a fully automatic gridding method, previously proposed by the authors' research group, is presented. the NVIDIA CUDA architecture was utilized in order to achieve parallel computation of complex steps of the algorithm. Experimental results showed that the proposed approach provides enhanced performance in terms of computational time, while achieving higher utilization of the available computational resources.

关键词： DNA computational complexity graphics processing units medical image processing parallel algorithms parallel architectures

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Design of array signal processing system based on TMS320C6678

Design of array signal processing system based on TMS320C667...

引用

5th IEEE international conference on Intelligent Networking and Collaborative Systems, INCoS 2013

作者： Li, Xiangyang Department of Computer Science Guangdong AIB Polytechnic College Guangzhou China

ISBN: (纸本)9780769549880

While the traditional single-processor system can not meet the requirements of modern array signal system, a new high-speed parallel system based on DSPs and FPGA is designed. the system complies with VITA 46 standard. the paper introduces the system design in detail, including system architecture, DSP subsystem and FPGA subsystem. the system based on TMS320C6678 can apply widely in the voice processing, sonar, radar, communication, real-time image processing and other high-speed signal processing fields. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A MILP formulation for a batch scheduling problem on parallel machines in the aircraft industry

A MILP formulation for a batch scheduling problem on paralle...

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5th international conference on Modeling, Simulation and Applied Optimization (ICMSAO)

作者： Boccia, Maurizio Bruno, Giuseppe Sterle, Claudio Univ Sannio Dept Engn Benevento Italy Univ Naples Federico II Dept Ind Engn Naples Italy Univ Naples Federico II Dept Elect Engn Naples Italy

ISBN: (纸本)9781467358149;9781467358125

In the aircraft industry structural components, referred to as part numbers (PN), have to be subject to an heat treatment in capacitated burn-in furnaces for a pre-defined period (exposure time) in order to provide them with specific physic and chemical features (e.g. hardness, corrosion resistance, conductivity). Two or more part numbers can be grouped in a batch and treated simultaneously in the same furnace if it is possible to individuate a common exposure time. In order to minimize the total completion time (makespan) of the process it needs to determine the appropriate grouping of the part numbers into batches (batching problem) to be processed by each furnace (scheduling problem). the problem can be modeled as a batch scheduling problem on parallel machines where the batching and the scheduling problem are considered at the same time. Starting from a real case study, we present an original integer linear programming formulation in the case of two capacitated parallel machines and we provide the results obtained on two real instances coming from the aircraft industry.

关键词： aerospace industry aircraft batch processing (industrial) furnaces integer programming linear programming parallel machines scheduling

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Accelerating the Performance of Stochastic Encoding-based Computations by Sharing Bits in Consecutive Bit Streams

Accelerating the Performance of Stochastic Encoding-based Co...

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IEEE 24th international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Li, Peng Lilja, David J. Univ Minnesota Dept Elect & Comp Engn Duluth MN 55812 USA

ISBN: (纸本)9781479904945;9781479904938

Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example, for most digital image processing algorithms, we need a 512-bit stream to represent an 8-bit pixel value stochastically to guarantee that the final computation error is less than 5%. To solve this issue, this paper proposes to share bits between adjacent bit streams to represent adjacent deterministic values. For example, in image processing applications, the bit stream which represents the current pixel value can share parts of the bits in the bit stream which represents the previous pixel value. We use an image contrast stretching algorithm to evaluate this method. Our experimental results show that the proposed methods can improve the performance by 90%.

关键词： Computer reliability fault tolerance logic design stochastic computing digital image processing

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Vectorized Higher Order Finite Difference Kernels

Vectorized Higher Order Finite Difference Kernels

引用

11th international conference on Applied parallel and Scientific Computing (PARA)

作者： Zumbusch, Gerhard Univ Jena Inst Angew Math D-07743 Jena Germany

ISBN: (纸本)9783642368035

Several highly optimized implementations of Finite Difference schemes are discussed. the combination of vectorization and an interleaved data layout, spatial and temporal loop tiling algorithms, loop unrolling, and parameter tuning lead to efficient computational kernels in one to three spatial dimensions, truncation errors of order two to twelve, and isotropic and compact anisotropic stencils. the kernels are implemented on and tuned for several processor architectures like recent Intel Sandy Bridge, Ivy Bridge and AMD Bulldozer CPU cores, all with AVX vector instructions as well as Nvidia Kepler and Fermi and AMD Southern and Northern Islands GPU architectures, as well as some older architectures for comparison. the kernels are either based on a cache aware spatial loop or on time-slicing to compute several time steps at once. Furthermore, vector components can either be independent, grouped in short vectors of SSE, AVX or GPU warp size or in larger virtual vectors with explicit synchronization. the optimal choice of the algorithm and its parameters depend both on the Finite Difference stencil and on the processor architecture.

关键词： Graphics processing unit

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Hardware Implementation of LU Decomposition Using Dataflow Architecture on FPGA

Hardware Implementation of LU Decomposition Using Dataflow A...

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5th international conference on Computer Science and Information Technology (CSIT)

作者： Eljammaly, Mahmoud Hanafy, Yasser Wahdan, Abdelmoniem Bayoumi, Amr Arab Acad Sci & Technol & Maritime Transport Cairo Egypt

ISBN: (纸本)9781467358255

Recent FPGA technology advances permitted the hardware implementation of selected software functions to enhance programs performance. Most of the work done was only concerned with integer operations. Little effort addressed floating point operations. In this paper we propose a dataflow implementation of the LU decomposition on FPGA.A modified Kernighan-Lin based task partitioning and assignment algorithm is presented in this paper. the algorithm showed acceptable improvement over existing techniques.

关键词： LU factorization tagged-token dataflow architecture FPGA Kernighan-Lin algorithm parallel processing

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PSIS: parallel semantic indexing system-preliminary experiments

PSIS: Parallel semantic indexing system-preliminary experime...

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13th international conference on algorithms and architectures for parallel processing, ICA3PP 2013

作者： Amato, Flora Gargiulo, Francesco Moscato, Vincenzo Persia, Fabio Picariello, Antonio University of Naples Federico II Dipartimento di Ingegneria Elettrica e Tecnologie Dell'Informazione via Claudio 21 80125 Naples Italy Italy

ISBN: (纸本)9783319038889

In this paper, we address the problem of defining a semantic indexing techniques based on RDF triples. In particular, we define algorithms for: i) defining clustering techniques of semantically similar RDF triplets;ii) defining algorithms for inserting, deleting and searching on a K-d based semantic tree built on the base of such clusterings;iii) defining a parallel implementation of the search algorithms. Preliminary experiments runned on a GRID-based parallel machines are designed and preliminary implemented and discusses, showing the performances of the proposed system. © Springer international Publishing Switzerland 2013.

关键词： Resource Description Framework (RDF)

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Model-Driven Approach for Supporting the Mapping of parallel algorithms to parallel Computing Platforms

Model-Driven Approach for Supporting the Mapping of Parallel...

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ACM/IEEE 16th international conference on Model-Driven Engineering Languages and Systems (MODELS)

作者： Arkin, Ethem Tekinerdogan, Bedir Imre, Kayhan M. Hacettepe Univ Dept Comp Engn Ankara Turkey

ISBN: (纸本)9783642415326;9783642415333

the trend from single processor to parallel computer architectures has increased the importance of parallel computing. To support parallel computing it is important to map parallel algorithms to a computing platform that consists of multiple parallel processing nodes. In general different alternative mappings can be defined that perform differently with respect to the quality requirements for power consumption, efficiency and memory usage. the mapping process can be carried out manually for platforms with a limited number of processing nodes. However, for exascale computing in which hundreds of thousands of processing nodes are applied, the mapping process soon becomes intractable. To assist the parallel computing engineer we provide a model-driven approach to analyze, model, and select feasible mappings. We describe the developed toolset that implements the corresponding approach together with the required metamodels and model transformations. We illustrate our approach for the well-known complete exchange algorithm in parallel computing.

关键词： Model Driven Software Development parallel Computing High Performance Computing Domain Specific Language Tool Support

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