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QbDJ: A Novel Framework for Handling Skew in parallel Join processing on Distributed Memory

QbDJ: A Novel Framework for Handling Skew in Parallel Join P...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Long Cheng Spyros Kotoulas Tomas E. Ward Georgios theodoropoulos National University of Ireland Maynooth Ireland IBM Res. Dublin Ireland Durham University UK

the performance of parallel distributed data management systems becomes increasingly important with the rise of Big Data. parallel joins have been widely studied both in the parallel processing and the database communities. Nevertheless, most of the algorithms so far developed do not consider the data skew, which naturally exists in various applications. State of the art methods designed to handle this problem are based on extensions to either of the two prevalent conventional approaches to parallel joins - the hash-based and duplication-based frameworks. In this paper, we introduce a novel parallel join framework, query-based distributed join (QbDJ), for handling data skew on distributed architectures. Further, we present an efficient implementation of the method based on the asynchronous partitioned global address space (APGAS) parallel programming model. We evaluate the performance of our approach on a cluster of 192 cores (16 nodes) and datasets of 1 billion tuples with different skews. the results show that the method is scalable, and also runs faster with less network communication compared to state-of-art PRPD approach in [1] under high data skew.

关键词： Arrays Distributed databases Histograms parallel processing Instruction sets Probes Silicon

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Sifting of a Potent Convex Hull Algorithm for Scattered Point Set Using parallel Programming

Sifting of a Potent Convex Hull Algorithm for Scattered Poin...

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international conference on Computational Intelligence and Communication Networks (CICN)

作者： Amitkumar S. Manekar Malti Nagle Pankaj Kawadkar Hitesh Gupta Research Scholar PIES Bhopal M.P India HOD IT PCST Bhopal M.P India HOD CSE PIES Bhopal M.P India HOD CSE PCST Bhopal M.P India

Geographic Information Systems (GIS) has been prominently working for the designed to sculpt the world. With the growth and data and increasing sophistication of analysis and processing techniques the traditional sequential methods of performing GIS processing on desktop computers is insufficient. this paper is based on analysis and the performance of 3D convex hull algorithm for the three flavors of parallel architecture considering spatial scatter point data using parallel programming. As GIS use huge set of scatter data for processing and development of many product, a Convex Hull of planner scattered point set will useful in the area of planning and grafting the satellite image in GIS. Analysis is based on the parallel algorithm on OpenMP, MPI and Hybrid of HPC (High Performance Computing) architecture also improvement strategy for the huge data point available for computing such as GIS spatial data with respective OpenMP, MPI and Hybrid is stated.

关键词： Algorithm design and analysis parallel processing three-dimensional displays Message systems Geographic information systems Runtime Spatial databases

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Loop level speculation in a task based programming model

Loop level speculation in a task based programming model

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international conference on High Performance Computing

作者： Rahulkumar Gayatri Rosa. M Badia Eduard Aygaude Barcelona Supercomputing Center Barcelona Spain

Uncountable loops (such as while loops in C) and if-conditions are some of the most common constructs in programming. While-loops are widely used to determine the convergence in linear algebra algorithms or goal finding problems from graph algorithms, to name a few. In general while-loops are used whenever the loop iteration space, the number of iterations a loop executes is unknown. Usually in while-loops, the execution of the next iteration is decided inside the current loop iteration (i.e. the execution of iteration i depends on the values computed in iteration i-1). this precludes their parallel execution in today's ubiquitous multi-core architectures. In this paper a technique to speculatively create parallel tasks from the next iterations before the current one completes is proposed. If consecutive loop-iterations are only control dependent, then multiple iterations can be executed simultaneously; later in the execution path, the runtime system will decide to either commit the results of such speculatively executed iterations or undo the changes made by them. Data dependences within or between non-speculative and speculative work are honored to guarantee correctness. the proposed technique is implemented in SMPSs, a task-based dataflow programming model for shared-memory multiprocessor architectures. the approach is evaluated on a set of applications from graph algorithms and linear algebra. Results are promising with an average increase in the speedup of 1.2x with 16 threads when compared to non speculative execution of the applications. the increase in the speedup is significant, since the performance gain is achieved over an already parallelized version of the benchmarks.

关键词： Runtime Synchronization Cascading style sheets parallel processing Computer architecture Instruction sets Programming

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Cyrus: Unintrusive Application-Level Record-Replay for Replay parallelism 13

Cyrus: Unintrusive Application-Level Record-Replay for Repla...

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18th international conference on Architectural Support for Programming Languages and Operating Systems

作者： Honarmand, Nima Dautenhahn, Nathan Torrellas, Josep King, Samuel T. Pokam, Gilles Pereira, Cristiano Univ Illinois Dept Comp Sci Urbana IL 61801 USA Intel Santa Clara CA USA

ISBN: (纸本)9781450318709

architectures for deterministic record-replay (R&R) of multi-threaded code are attractive for program debugging, intrusion analysis, and fault-tolerance uses. However, very few of the proposed designs have focused on maximizing replay speed - a key enabling property of these systems. the few efforts that focus on replay speed require intrusive hardware or software modifications, or target whole-system R&R rather than the more useful application-level R&R. this paper presents the first hardware-based scheme for unintrusive, application-level R&R that explicitly targets high replay speed. Our scheme, called Cyrus, requires no modification to commodity snoopy cache coherence. It introduces the concept of an on the-fly software Backend Pass during recording which, as the log is being generated, transforms it for high replay parallelism. this pass also fixes-up the log, and can flexibly trade-off replay parallelism for log size. We analyze the performance of Cyrus using full system (OS plus hardware) simulation. Our results show that Cyrus has negligible recording overhead. In addition, for 8-processor runs of SPLASH-2, Cyrus attains an average replay parallelism of 5, and a replay speed that is, on average, only about 50% lower than the recording speed.

关键词： Deterministic Replay Application-level parallel Replay Unintrusive Hardware-Assisted Recording Source-only Recording Backend Log processing

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Hardware Implementation of LU Decomposition Using Dataflow Architecture on FPGA

Hardware Implementation of LU Decomposition Using Dataflow A...

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international conference on Computer Science and Information Technology

作者： Mahmoud Eljammaly Yasser Hanafy Abdelmoniem Wahdan Amr Bayoumi Arab Academy for Science and Technology and Maritime Transport Cairo Egypt.

ISBN: (纸本)9781467356107

Recent FPGA technology advances permitted the hardware implementation of selected software functions to enhance programs performance. Most of the work done was only concerned with integer operations. Little effort addressed floating point operations. In this paper we propose a dataflow implementation of the LU decomposition on FPGA.A modified Kernighan-Lin based task partitioning and assignment algorithm is presented in this paper. the algorithm showed acceptable improvement over existing techniques.

关键词： LU factorization tagged-token dataflow architecture FPGA Kernighan-Lin algorithm parallel processing. Field programmable gate arrays LU decomposition data flow architecture parallel processing (COMPUTERS) floating point arithmetic Allocation Algorithm Computer hardware

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Efficient hardware calculation of running statistics

Efficient hardware calculation of running statistics

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international conference on Image and Vision Computing New Zealand, IVCNZ

作者： Donald G. Bailey Michael J. Klaiber School of Engineering and Advanced Technology Massey University Palmerston North Institute for Parallel and Distributed Systems University of Stuttgart

Calculation of mean, variance and standard deviation are often required for segmentation or feature extraction. In image processing, often an integer approximation is adequate. Conventional methods require division and square root operations, which are expensive to realize in hardware in terms of both the amount of required resources and latency. A new class of iterative algorithms is developed based on integer arithmetic. An implementation of the algorithms as a hardware architecture for a Field-Programmable Gate Array (FPGA) is compared with architectures using the conventional approach, which shows a significantly reduced latency while using less hardware resources.

关键词： Hardware Computer architecture Standards Approximation methods Nickel Accuracy Feature extraction

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Marıa del Carmen Calatrava Moreno thomas Auzinger Technische Universitat Wien Wien Wien AT Institute of Computer Graphics and Algorithms Vienna University of Technology Vienna Austria

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing units Hardware Computer architecture Graphics Instruction sets Computational modeling Semiconductor optical amplifiers

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parallel Verification of UML Using DiVinE Tool

Parallel Verification of UML Using DiVinE Tool

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international conference on Computer Science and Information Technology

作者： Muhammad Abdul Basit-Ur-Rahim Jamil Ahmad Fahim Arif Department of Computer Software Engineering Military College of Signals National University of Science & Technology Islamabad Pakistan Research Center for Modeling and Simulation Military College of Signals National University of Science & Technology Islamabad Pakistan

ISBN: (纸本)9781467356107

Unified Modeling Language is being used for modeling of business processes, real-time systems, embedded systems and hybrid systems. In software engineering, there are different techniques for verification of such systems. Model checking is one of the techniques for the automatic verification of software models. Earlier, these model were verified by sequential model checking tools. For very large complex systems, parallel verification can save verification time. DiVinE is a model checking tool for both CPUs and GPUs clusters to perform parallel linear time logic (LTL) verification of systems. In this paper, we propose a parallel verification methodology for UML models using DiVinE tool. We explain this methodology by the case study example of fuel filling machine.

关键词： UML Verification DiVinE parallel Verification UML Verification checking tools central processing units parallel Lines Complex systems hybrid systems Model checking Business process management Software engineering program verification modelling languages FILLING MACHINE Case studies

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Multi-core Computation of Transfer Matrices for Strip Lattices in the Potts Model

Multi-core Computation of Transfer Matrices for Strip Lattic...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Cristobal A. Navarro Nancy Hitschfeld Fabrizio Canfora Department of Computer Science Universidad de Chile Santiago Valdivia Chile Centro de Estudios Cientifícos (CECs) Valdivia Chile Department of Computer Science Universidad de Chile Santiago Chile

the transfer-matrix technique is a convenient way for studying strip lattices in the Potts model since the computational costs depend just on the periodic part of the lattice and not on the whole. However, even when the cost is reduced, the transfer-matrix technique is still an NP-hard problem since the time T (|V |, |E|) needed to compute the matrix grows exponentially as a function of the graph width. In this work, we present a parallel transfer-matrix implementation that scales performance under multi-core architectures. the construction of the matrix is based on several repetitions of the deletion-contraction technique, allowing parallelism suitable to multi-core machines. Our experimental results show that the multi-core implementation achieves speedups of 3.7X with p = 4 processors and 5.7X with p = 8. the efficiency of the implementation lies between 60% and 95%, achieving the best balance of speedup and efficiency at p = 4 processors for actual multi-core architectures. the algorithm also takes advantage of the lattice symmetry, making the transfer matrix computation to run up to 2X faster than its non-symmetric counterpart and use up to a quarter of the original space.

关键词： Lattices Strips Program processors Computational modeling Partitioning algorithms parallel processing Buildings

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Accelerating the Performance of Stochastic Encoding-based Computations by Sharing Bits in Consecutive Bit Streams

Accelerating the Performance of Stochastic Encoding-based Co...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Peng Li David J. Lilja Department of Electrical and Computer Engineering University of Minnesota Twin Cities Minneapolis MN USA 55812

ISBN: (纸本)9781479904945

Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example, for most digital image processing algorithms, we need a 512-bit stream to represent an 8-bit pixel value stochastically to guarantee that the final computation error is less than 5%. To solve this issue, this paper proposes to share bits between adjacent bit streams to represent adjacent deterministic values. For example, in image processing applications, the bit stream which represents the current pixel value can share parts of the bits in the bit stream which represents the previous pixel value. We use an image contrast stretching algorithm to evaluate this method. Our experimental results show that the proposed methods can improve the performance by 90%.

关键词： Computer reliability fault tolerance logic design stochastic computing digital image processing bit stream Image processing Logic design Fault tolerance Drill bits IMAGE CONTRAST arithmetic errors image processing algorithm streams random fluctuations processing time Binary digits

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