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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3294 条记录，以下是1661-1670 订阅

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Power Optimization of Sum-of-Products Design for Signal processing Applications

Power Optimization of Sum-of-Products Design for Signal Proc...

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Seok Won Heo Suk Joong Huh Milo? D. Ercegovac Computer Science Department University of California at Los Angeles CA USA 90095 Samsung Electronics Suwon Korea

ISBN: (纸本)9781479904945

Power consumption is a critical aspect in today's mobile environment, while high-throughput remains a major design goal. To satisfy both low-power and high-throughput requirements, parallelism has been employed. In this paper we present an approach to reducing power dissipation in the design of sum-of-products operation by utilizing parallel hardware while maintaining high-throughput. the proposed design reduces about 46% of execution time with about 12% energy penalty compared to the ARM7TDMI-S multipliers in benchmark programs.

关键词： Low-power Arithmetic High-throughput Arithmetic Sum-of-products

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A Highly Efficient, thread-Safe Software Cache Implementation for Tightly-Coupled Multicore Clusters

A Highly Efficient, Thread-Safe Software Cache Implementatio...

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Christian Pinto Luca Benini DEI Department - University of Bologna Bologna Viale Risogimento 2 Italy

ISBN: (纸本)9781479904945

A widely adopted design paradigm for many-core accelerators features processing elements grouped in clusters. Due to area, power and design simplicity, processors in the same clusters are often not equipped with data-caches but rather share a tightly coupled data memory (TCDM). Even if the use of a TCDM is more energy and area efficient than a cache it requires a higher programming effort because memory needs to be explicitly managed with DMA-based L3 to TCDM copies. In this context Software Caches can be used to automatically transfer data between the local TCDM and the external memory, simplifying the task of the programmer. In this paper we present an implementation of Software Cache for the STMicroelectronics SthORM many-core accelerator, featuring a L1 TCDM shared by 16 processors in a cluster. Our main contribution is the design of a fast and thread-safe cache allowing parallel access from different processing elements inside the same cluster. We evaluate our implementation with micro-benchmarks as well as a real world application from the computer vision domain. Results show that a software cache provides major performance improvements with respect to L3 allocation of large data structures even when it is aggressively shared among many parallel threads.

关键词： TCDM SthORM Multicore Clusters Cache memory tight coupling performance boost processing Element computer software external memory computer programs Computer personnel Multi-core processors Layer 3 (network layer)

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parallel pattern mining on Graphics processing Units

Parallel pattern mining on Graphics Processing Units

引用

international Carpathian Control conference (ICCC)

作者： Krzysztof Hryniów Institute of Control and Industrial Electronics Warsaw University of Technology Warsaw Poland

ISBN: (纸本)9781467344883

Frequent pattern mining is a field with many practical applications, where large computational power and speed are needed. Many state-of-the-art frequent pattern mining applications are an inefficient solutions for both shared memory and multiprocessor systems due to problems with parallelism and memory. One of possible solutions to the problem is the use of Graphics processing Unit (GPU) in the system along with modification of classical pattern mining algorithms in such a way, that the sequential part of algorithm is run on host and the parallel part on GPU. Such solution allows for considerable speed-up (of up to two orders of magnitude), but for more complicated problems and FPM algorithms it can be hard to achieve. So far there were presented 3 modifications of the most basic Apriori algorithm for solving GPGPU (general-purpose computation on graphics hardware) problems. Each of proposed parallel implementations (PBI, TBI, GPA) is suited only for frequent itemset mining, furthermore even the best of them (TBI) obtains results only 2-5 times faster then CPU-based versions of FP-growth algorithm. On ICCC'12 there was presented parallel version of more complex GSP algorithm adjusted for GPGPU problems, capable of obtaining results 50-100 times faster then CPU-based version, with the same accuracy. Not only is the GPGPU implementation the fastest, but also it is suited for solving more complex frequent pattern mining problems. this paper presents extension of proposed modifications to more complex algorithms from Apriori family. the modifications are evaluated both theoretically and with use of experimental setup consisting of nVidia Tesla card and CUDA parallel computing platform. Solution proposed in the paper uses more complex, faster frequent pattern mining algorithms then GSP, making it well suited for solving real-time GPGPU problems for very large data sets.

关键词： Graphics processing units Data mining Databases Kernel Resource management Real-time systems Memory management

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A Self-Organizing Architecture for Cloud by Means of Infrastructure Performance and Event Data

A Self-Organizing Architecture for Cloud by Means of Infrast...

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IEEE international conference on Cloud Computing Technology and Science (CloudCom)

作者： Martin Serrano Manfred Hauswirth Nikos Kefalakis John Soldatos Digital Enterprise Research Institute DERI - NUI Galway Galway Ireland Athens Institute of Technology AIT Athens Greece

the management performance of cloud systems is measured by the capacity of the cloud for controlling virtual infrastructures and their capability to run parallel-computing applications and distributed-processing services independently. the challenge about how this management performance can be done more dynamically (self-organization) by means of distributed user data and application data demands is yet an area to explore. this paper introduces first a functional architecture design, following the principles for cloud-based service lifecycle control and service composition in cloud, and second an in-house approach enabling self-organization for cloud services controlling the installation of virtual machines by using event-driven management operations acting as a proof of concept implementation. From a management point of view in cloud, enabling control of virtual infrastructures as a response to performance protocols by means of event(s) data processing is fundamental. Likewise managing cloud services lifecycle by enabling scalable applications and using distributed information systems and linked data processing, guarantee the self-organizing feature for cloud systems. Finally multiple advantages arise when infrastructure performance and end user data are used in cloud service management as it is discussed in this paper.

关键词： Cloud computing Data models Computer architecture Service-oriented architecture Adaptation models Distributed databases Data processing

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A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing

A Reconfigurable Application-specific Instruction-set Proces...

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Waqar Hussain Xiaolin Chen Gerd Ascheid Jari Nurmi Department of Electronics and Communications Engineering Tampere University of Technology FI-33101 Tampere Finland Institute for Communication Technologies and Embedded Systems Rheinisch-Westfaelische Technische Hochschule DE-52070 Aachen Germany

ISBN: (纸本)9781479904945

In this paper, we have presented a Reconfigurable Application-specific Instruction-set Processor (rASIP) that processes mixed-radix(2, 4) 64 and 128-point Fast Fourier Transform (FFT) algorithms while satisfying the partial execution-time requirements of IEEE-802.11n standard. the rASIP was designed by integrating a template-based Coarse-Grain Reconfigurable Array (CGRA) in the datapath of a simple Reduced Instruction-Set Computing (RISC) Processor. the instruction set of the RISC processor was extended to add special instructions to enable cycle-accurate processing by the CGRA. the rASIP is synthesized for Field Programmable Gate Arrays for the measurement of resource utilization and execution time. the postfit gate-level netlist of rASIP was simulated to estimate the power and energy consumption. Based on our measurements and estimates, we have studied the advantages of using rASIP in comparison with other systems.

关键词： CGRA RISC rASIP Coarse-grained Reconfigurable Architecture RNA-Induced Silencing Complex Reduced instruction set computers RISC processors Field programmable gate arrays Fast Fourier transform configurability PROCESSOR Resource utilization execution time instruction

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Transforming A Linear Algebra Core to An FFT Accelerator

Transforming A Linear Algebra Core to An FFT Accelerator

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Ardavan Pedram John McCalpin Andreas Gerstlauer Department of Electrical and Computer Engineering Texas Advanced Computing Center The University of Texas at Austin

ISBN: (纸本)9781479904945

this paper considers the modifications required to transform a highly-efficient, specialized linear algebra core into an efficient engine for computing Fast Fourier Transforms (FFTs). We review the minimal changes required to support Radix-4 FFT computations and propose extensions to the micro-architecture of the baseline linear algebra core. Along the way, we study the critical differences between the two classes of algorithms. Special attention is paid to the configuration of the on-chip memory system to support high utilization. We examine design trade-offs between efficiency, specialization and flexibility, and their effects both on the core and memory hierarchy for a unified design as compared to dedicated accelerators for each application. the final design is a flexible architecture that can perform both classes of applications. Results show that the proposed hybrid FFT/Linear Algebra core can achieve 26.6 GFLOPS/S with a power efficiency of 40 GFLOPS/W, which is up to 100× and 40× more energy efficient than cutting-edge CPUs and GPUs, respectively.

关键词： CPUs FFT GFLOPS/S Fast Fourier transform central processing units Linear algebra core dynamic efficiency memory hierarchy

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Remote image processing technology based on matlab web server

Remote image processing technology based on matlab web serve...

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2013 5th international conference on Computational and Information Sciences, ICCIS 2013

作者： Sun, Chengfu Sun, Chengcai Equipment Management Department Zhejiang Energy Jiaxing Power Generation Co. Ltd Jiaxing China Municipal and Environmental Engineering College Shenyang Jianzhu University Shenyang China

ISBN: (纸本)9780769550046

In this paper a new method of remote image processing technology based on MATLAB Web Server is proposed. through the Internet, we create a remote image processing system, modify the m-file which can only be executed in local computer and put it in the server. the graphical user interface provides input data and shows results. It can achieve remote executing the MATLAB program and the relevant m-file in the server and return the results. the designed remote computer vision system can process images and other information transmitted from the client. It can be used to analyze multiple types of data, being multithreaded execution and multi-user parallel used. © 2013 IEEE.

关键词： Graphical user interfaces

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Performance Analysis and Optimization of the Tiled Cholesky Factorization on NUMA Machines

Performance Analysis and Optimization of the Tiled Cholesky ...

引用

5th international Symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Jeannot, Emmanuel Inria Bordeaux Sud Ouest LaBRI Bordeaux France

We discuss some performance issues of the tiled Cholesky factorization on non-uniform memory access-time (NUMA) shared memory machines. We show how to optimize thread placement and data placement in order to achieve p... 详细信息

ISBN: (纸本)9780769548982;9781467345668

关键词： matrix decomposition parallel processing performance evaluation shared memory systems

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Sparse Matrix-Vector Multiplication Based on Network-on-Chip: On Data Mapping

Sparse Matrix-Vector Multiplication Based on Network-on-Chip...

引用

5th international Symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Mansour, Ahmad Goetze, Juergen TU Dortmund Informat Proc Lab Dortmund Germany

ISBN: (纸本)9780769548982;9781467345668

Sparse Matrix-Vector Multiplication (SMVM) on parallel hardware is a very sophisticated problem because of the irregular data communication requirements. the communication volume in the parallel hardware is determined by how data is distributed among the processing elements. In this paper we introduce two methods of data mapping for SMVM based on Network-on-Chip (NoC) in order to spread the load among its components. Later, we introduce the effect of recordering of the sparse matrix on those mapping methods. Simulations are performed using an OMNet++ based NoC simulator.

关键词： data communication network-on-chip parallel processing public domain software sparse matrices

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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