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An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-core architectures

An Adaptive Block Pinning Cache for Reducing Network Traffic...

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international conference on Computational Intelligence and Communication Networks (CICN)

作者： Nitin Chaturvedi S. Gurunarayanan Electrical Electronics Engineering Department Birla Institute of Technology and Science Pilani India

With advent of new technologies there is exponential increase in multi-core processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this issue. A NUCA partitions the complete cache memory into smaller multiple banks and allows banks near the processor cores to have lower access latencies than those further away, thus reducing the effects of the cache's internal wire delays. Traditionally, NUCA organizations have been classified as static (S-NUCA) and dynamic (D- NUCA). While in S-NUCA a data block is mapped to a unique bank in the NUCA cache, D-NUCA allows a data block to be mapped in multiple banks. In D-NUCA designs a data blocks can migrate towards the processor core that access them most frequently. this migration of data blocks will increase network traffic. the short life time of data blocks and low spatial locality in many applications results in eviction of block with few unused words. this effectively increases miss rate, and waste on chip network bandwidth. Unused word transfers also wastes a large fraction of on chip energy *** this paper, we present an efficient and implementable cache design that eliminate unnecessary coherence traffic and match data movements to an applications spatial locality. It also presents one way to scale on-chip coherence with less costeffective techniques such as shared caches augmented to track cached copies, explicit eviction notification and hierarchal design. Based on our scalability analysis of this cache design we predict that this design consistently reduce miss rate and improve the fraction of data transmitted that is actually utilized by the application.

关键词： Coherence Arrays Protocols Bandwidth Multicore processing Hardware

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PAAG: A Polymorphic Array Architecture for Graphics and Image processing

PAAG: A Polymorphic Array Architecture for Graphics and Imag...

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5th international Symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Li, Tao Xiao, Lingzhi Huang, Hucai Han, Jungang XiAn Univ Posts & Telecom Res Ctr Telecom ASIC Design Xian Peoples R China XiAn Univ Posts & Telecom Sch Comp Sci Xian Peoples R China

ISBN: (纸本)9780769548982;9781467345668

A novel, polymorphic array architecture is proposed in this paper. this architecture is capable of supporting a dynamic mixture of data parallel computation (DLP), thread level parallel computation (TLP), and operation level parallel computation (OLP). We aim at designing a programmable architecture that can approach ASIC performance. this is accomplished through new architectural features and implementation level innovations. the architecture and its implementation are presented in the paper to demonstrate its feasibility and capabilities.

关键词： parallel computation polymorphic architecture data parallelism thread level parallelism operation level parallelism thread scheduling message routin.g

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Restricted duplication based MILP formulation for scheduling task graphs on unrelated parallel machines

Restricted duplication based MILP formulation for scheduling...

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5th international Symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Singh, Jagpreet Mangipudi, Bhargav Betha, Sandeep Auluck, Nitin Indian Inst Technol Ropar Dept Comp Sci & Engn Rupnagar 140001 India

ISBN: (纸本)9780769548982;9781467345668

Duplication has proved to be a vital technique for scheduling task graphs on a network of unrelated parallel machines. Few attempts have been made to model duplication in a Mixed Integer Linear Program (MILP) to reduce schedule length. Other known optimal MILPs duplicate a job on all the available processing elements and this increases their complexities. this paper proposes a new REStricted Duplication (RESDMILP) approach to model duplication in a MILP. the complexity of this model increases with the increase in the amount of duplication. Experiments conducted have revealed that RESDMILP achieves better runtimes when the problem instance is solved optimally and provides better lower bound and percentage gap if it is run for a fixed amount of time. the percentage gap is defined as, (UB-LB)/UB where UB and LB are the upper and lower bounds achieved by the MILPs respectively.

关键词： MILP Scheduling Heterogeneous Duplication Multiprocessors

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An Automatic parallel-Stage Decoupled Software Pipelining parallelization Algorithm Based on OpenMP

An Automatic Parallel-Stage Decoupled Software Pipelining Pa...

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IEEE international conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Xiaoxian Liu Rongcai Zhao Lin Han Peng Liu State Key Laboratory of Mathematical Engineering and Advanced Computing Zhengzhou China

ISBN: (纸本)9781479914449

While multicore processors increase throughput for multi-programmed and multithreaded codes, many important applications are single threaded and thus do not benefit. Automatic parallelization techniques play an important role in migrating singe threaded applications to multicore platforms. Unfortunately, the prevalence of control flow, recursive data structures, and general pointer accesses in ordinary programs renders the traditional automatic parallelization techniques unsuitable. parallel-Stage Decoupled Software Pipelining (PS-DSWP) is proposed to exploit fine-grained pipeline parallelism lurking in ordinary programs with the existence of all kinds of dependences, including arbitrary control dependences, at the instruction level. But it requires knowledge of architectural properties and hardware support of a communication channel and two special instructions. We propose an improved PS-DSWP algorithm based on OpenMP in this paper. It is implemented without relying on CPU architectures by using a high level intermediate representation. Moreover, the Program Dependence Graph (PDG) used in the algorithm is built based on the basic blocks, which exploits coarser-grained parallelism than the original PS-DSWP transformation with PDG based on instructions. OpenMP is employed in our algorithm to assign task and implement synchronization among threads while avoiding dependence on hardware support. We evaluate the loops with complex memory patterns and control flow, which cannot be dealt with by traditional techniques, on multicore platform. As a result, they can be parallelized and gain significant performance improvement with our algorithm. We obtain a maximum speedup as high as 2.07x and on average 1.39x with 5 threads.

关键词： Instruction sets Synchronization Pipeline processing Multicore processing Merging

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SPD-RAID4: Splitting Parity Disk for RAID4 Structured parallel SSD Arrays

SPD-RAID4: Splitting Parity Disk for RAID4 Structured Parall...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Wen Pan Feng Liu Tao Xie Yanyan Gao Yiming Ouyang Tian Chen Computer & Information School Hefei University of Technology Hefei Anhui China Computer Science Department San Diego State University San Diego California USA

Data-intensive applications like video processing and bioinformatics increasingly demand a high-performance and highly reliable storage system. Hard disk drive (HDD) has long been used as a standard storage device for most existing storage systems. Recently, NAND-flash memory based solid state drives (SSDs) are gradually exploited to replace HDDs in enterprise computing infrastructures due to their salient features such as high performance, low power consumption, and excellent shock-resistance. With rapid price decreasing and capacity increasing, flash SSD based disk arrays organized in some RAID structures become feasible and greatly needed. In this paper, we propose a new RAID4 architecture called SPD-RAID4 (Splitting Parity Disk - RAID4) for parallel SSD arrays. It splits the parity disk of a traditional RAID 4 array into configurable number of smaller ones. thus, multiple small parity SSDs operate in tandem with data SSDs to achieve a high performance and high level of reliability. We compare the performance of SPD-RAID4 with conventional RAID4 and RAID5 architectures by using both real-world traces and synthetic benchmarks. Experimental results demonstrate that in terms of mean response time SPD-RAID4 outperforms standard RAID5 structured SSD arrays by up to 20.3%. Compared with standard RAID4, SPD-RAID4 achieves a performance gain up to 40.6%.

关键词： Arrays Standards Reliability Time factors Flash memories Performance evaluation

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A Yoke of Oxen and a thousand Chickens for Heavy Lifting Graph processing 12

A Yoke of Oxen and a Thousand Chickens for Heavy Lifting Gra...

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21st international conference on parallel architectures and Compilation Techniques (PACT)

作者： Gharaibeh, Abdullah Costa, Lauro Beltrao Santos-Neto, Elizeu Ripeanu, Matei Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450311823

Large, real-world graphs are famously difficult to process efficiently. Not only they have a large memory footprint but most graph processing algorithms entail memory access patterns with poor locality, data-dependent parallelism, and a low compute-to-memory access ratio. Additionally, most real-world graphs have a low diameter and a highly heterogeneous node degree distribution. Partitioning these graphs and simultaneously achieve access locality and load-balancing is difficult if not impossible. this paper demonstrates the feasibility of graph processing on heterogeneous (i.e., including both CPUs and GPUs) platforms as a cost-effective approach towards addressing the graph processing challenges above. To this end, this work (i) presents and evaluates a performance model that estimates the achievable performance on heterogeneous platforms;(ii) introduces TOTEM - a processing engine based on the Bulk Synchronous parallel (BSP) model that offers a convenient environment to simplify the implementation of graph algorithms on heterogeneous platforms;and, (iii) demonstrates TOTEM'S efficiency by implementing and evaluating two graph algorithms (PageRank and breadth-first search). TOTEM achieves speedups close to the model's prediction, and applies a number of optimizations that enable linear speedups with respect to the share of the graph offloaded for processing to accelerators.

关键词： Heterogeneous Systems GPU Graph algorithms Breadth-first Search PageRank TOTEM

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Implementation and Optimization of Intra Prediction in H264 Video parallel Decoder on CUDA

Implementation and Optimization of Intra Prediction in H264 ...

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IEEE 5th international conference on Advanced Computational Intelligence (ICACI)

作者： Liu, Bocheng Chen, Qingkui Shanghai Univ Sci & Technol Sh 3101 Peoples R China

ISBN: (纸本)9781467317443

In order to analyze the quality of the massive H264 videos in the 3G network, we set up a GPU cluster to decode the multi-videos on CUDA and evaluated the clarities of the decoded frames. this paper focuses on parallel intra prediction and its optimization. By improving parallel algorithm, adjusting data structure and rationally using multilevel memories of GPU, we show that these operations achieve an average of 63.8% decrease of execution time comparing to original algorithm.

关键词： 3G mobile communication decoding graphics processing units parallel architectures video coding

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Application specific hardware architecture for high-throughput short-length LDPC decoders

Application specific hardware architecture for high-throughp...

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IEEE international conference on Intelligent Computer Communication and processing

作者： Bogdan Belean Sergiu Nedevschi Monica Borda National Institute for R&D of Isotopic and Molecular Technologies INCDTIM Computer Science Dept. Technical University of Cluj-Napoca Communication Dept. Technical University of Cluj-Napoca

ISBN: (纸本)9781479914920

LDPC codes have been intensively used in various wireless communication applications, due to their increased BER performance. the present paper summarizes the state of the art applications of short length LDPC codes and proposes FPGA based application specific hardware architectures for short-length LDPC decoders. the decoding algorithms considered for implementation are both belief propagation and min-sum algorithm. Due to the increased BER performances, the proposed architecture make use of parallel computation capabilities offered by FPGA technology in order to implement the belief propagation algorithm. In spite of the iterative nature and increased computational complexity of the LDPC decoding algorithm, the proposed architecture achieves high-throughput, mandatory in real-time application and data transmission. the architecture for the LDPC belief propagation based decoder is based on arctangent hyperbolic function approximation used for check nodes update.

关键词： LDPC codes FPGA Decoding algorithms Hardware implementations parallel computing

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GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence Alignment Algorithm

GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence A...

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19th international conference on High Performance Computing (HiPC)

作者： Narang, Ankur Soman, Jyothish Lahabar, Sheetal IBM India Res Labs Vasant Kunj Delhi 110070 India

ISBN: (纸本)9781467323703;9781467323727

Next Generation Sequencing (NGS) platforms typically produce short reads of size 50-150 base pairs (bp). the number of such short reads can be up to 6 billion per run. To align these short reads to a large genome is a computationally challenging problem. In this paper, we address this problem by considering the design and optimization of parallel sequence alignment on GPU based hybrid architectures. Even though the sequence alignment algorithm is inherently data-parallel, issues such as (a) space-time trade-offs in the Indexing schema, (b) need for fast candidate location search (CAL) on GPU, (c) maintaining low divergence along with low space for the dynamic programming based local alignment, make this a very challenging problem. We present the design of our novel parallel algorithm Graphics processor Accelerated BFAST (GrABFAST) for large scale read alignment that overcomes these challenges and demonstrates superior performance compared to Intel multicore architectures. Using 5 large genomes including those of Humans, Maize, Horse, Dog and Bacteria, we demonstrate a speedup of around 6x using Fermi Tesla C2070 GPUs vs the BFAST algorithm on 16 core Intel Xeon 5570 architecture.

关键词： dynamic programming graphics processing units multiprocessing systems parallel algorithms parallel architectures

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HPPC 2010: 5th Workshop on Highly parallel processing on a Chip

HPPC 2010: 5th Workshop on Highly Parallel Processing on a C...

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17th international Euro-Par conference on parallel processing

作者： Forsell, Martti Traff, Jesper Larsson Tech Res Ctr Finland VTT Oulu Finland Univ Vienna Fac Comp Sci Dept Comp Sci Vienna Austria

ISBN: (纸本)9783642297373;9783642297366

Despite the processor industry having more or less successfully invested already 10 years to develop better and increasingly parallel multicore architectures, both software community and educational institutions appear still to rely on the sequential computing paradigm as the primary mechanism for expressing the (very often originally inherently parallel) functionality, especially in the arena of general purpose computing. In that respect, parallel programming has remained a hobby of highly educated specialists and is still too often being considered as too difficult for the average programmer. Excuses are various: lack of education, lack of suitable easy-to-use tools, too architecture-dependent mechanisms, huge existing base of sequential legacy code, steep learning curves, and inefficient architectures. It is important for the scientific community to analyze the situation and understand whether the problem is with hardware architectures, software development tools and practices, or both. Although we would be tempted to answer this question (and actually try to do so elsewhere), there is strong need for wider academic discussion on these topics and presentation of research results in scientific workshops and conferences.

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