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检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3284 条记录，以下是161-170 订阅

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Supporting Energy-Efficient Computing on Heterogeneous CPU-GPU architectures 5

Supporting Energy-Efficient Computing on Heterogeneous CPU-G...

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IEEE 5th international conference on Future Internet of things and Cloud (FiCloud)

作者： Siehl, Kyle Zhao, Xinghui Washington State Univ Sch Engn & Comp Sci Vancouver WA 98686 USA

ISBN: (纸本)9781538620748

Modern high performance computing and cloud computing infrastructures often leverage Graphic processing Units (GPUs) to provide accelerated, massively parallel computational power. this performance gain, however, may also introduce higher energy consumption. the energy challenge has become more and more pronounced when the system scales. To address this challenge, we propose Archon, a framework for supporting energy-efficient computing on CPU-GPU heterogeneous architectures. Specifically, Archon takes user's programs as input, automatically distribute the workload between CPU and GPU, and dynamically tunes the distribution ratio at runtime for an energy-efficient execution. Experiments have been carried out to evaluate the effectiveness of Archon, and the results show that it can achieve considerable energy savings at runtime, without significant efforts from the programmers.

关键词： Energy Efficiency GPGPU Computing Heterogeneous architectures Hybrid Computing

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Efficient Computation of Spherical Harmonic Transform using parallel Architecture of CUDA

Efficient Computation of Spherical Harmonic Transform using ...

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5th international conference on Signal processing and Communication Systems (ICSPCS)

作者： Huang, Weiyu Khalid, Zubair Kennedy, Rodney A. Australian Natl Univ Coll Engn & Comp Sci Res Sch Engn Canberra ACT Australia

ISBN: (纸本)9781457711800

Spherical harmonics serve as basis functions on the unit sphere and spherical harmonic transform is required in analysis and processing of signals in the spectral domain. We investigate the possibility of parallel computation of spherical harmonic transform using Compute Unified Device Architecture (CUDA) with no communication between parallel kernels. We identify the parallel components in the widely used spherical harmonic transform method proposed by Driscoll and Healy. We provide the implementation details and compare the computational complexity with the sequential algorithm. For a given bandlimited signal with maximum spherical harmonics degree L, using the O(L) number of parallel processing kernels, we present that the spherical harmonic coefficients can be calculated in O(Llog(2) L) time as compared to O(L-2 log(2) L). For corroboration, we provide the simulation results using CUDA which indicate the reduction in computational complexity

关键词： parallel architectures spherical harmonic analysis Sphericity complexity classes Transform parallel processing (COMPUTERS) sequential algorithm Spectral domain Simulation results

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Independent performance modeling of parallel architectures and algorithms 5

Independent performance modeling of parallel architectures a...

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5th international conference on Computing and Information, ICCI 1993

作者： Johnson, E.E. Parallel Archit. Res. Lab. New Mexico State Univ. Las CrucesNM United States

ISBN: (纸本)0818642122

A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance prediction tools assist the system designer in initially selecting, and then modifying, both the algorithm and the architecture to obtain acceptable performance. In this paper, we present a modeling approach that permits separate evaluation of algorithm and architecture performance with only a small number of "cross" parameters required to link the two models. An example application of this technique to a Gaussian elimination algorithm on two dissimilar multiprocessor architectures shows good agreement with actual performance figures obtained from measurement and simulation. © 1993 IEEE.

关键词： parallel architectures

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Greed is Good: parallel algorithms for Bipartite-Graph Partial Coloring on Multicore architectures 46

Greed is Good: Parallel Algorithms for Bipartite-Graph Parti...

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46th international conference on parallel processing Workshops (ICPPW)

作者： Tas, Mustafa Kemal Kaya, Kamer Saule, Erik Sabanci Univ Comp Sci & Engn Istanbul Turkey Ohio State Univ Dept Biomed Informat Columbus OH 43210 USA Univ N Carolina Comp Sci Charlotte NC 28223 USA

ISBN: (纸本)9781538610428

In parallel computing, a valid graph coloring yields a lock-free processing of the colored tasks, data points, etc., without expensive synchronization mechanisms. However, coloring is not free and the overhead can be significant. In particular, for the bipartite-graph partial coloring (BGPC) and distance-2 graph coloring (D2GC) problems, which have various use-cases within the scientific computing and numerical optimization domains, the coloring overhead can be in the order of minutes with a single thread for many real-life graphs. In this work, we propose parallel algorithms for bipartite-graph partial coloring on shared-memory architectures. Compared to the existing shared-memory BGPC algorithms, the proposed ones employ greedier and more optimistic techniques that yield a better parallel coloring performance. In particular, on 16 cores, the proposed algorithms are more than 4x faster than their counterparts in the ColPack library which is, to the best of our knowledge, the only publicly-available coloring library for multicore architectures. In addition to BGPC, the proposed techniques are employed to devise parallel distance-2 graph coloring algorithms and similar performance improvements have been observed. Finally, we propose two costless balancing heuristics for BGPC that can reduce the skewness and imbalance on the cardinality of color sets (almost) for free. the heuristics can also be used for the D2GC problem and in general, they will probably yield a better color-based parallelization performance especially on many-core architectures.

关键词： Greedy graph coloring bipartite-graph coloring distance-2 coloring shared-memory parallel algorithms

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A VLSI architecture of EBCOT encoder for JPEG2000 5

A VLSI architecture of EBCOT encoder for JPEG2000

引用

5th international conference on ASIC

作者： Liu, LB Li, DJ Zhang, L Wang, ZH Chen, HY Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

ISBN: (纸本)078037889X

Embedded Block Coding with Optimized Truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. this paper proposes a VLSI architecture of EBCOT, in which a Dynamic Memory Control (DMC) strategy is used to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. this architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image&video applications.

关键词： VLSI data compression digital signal processing chips encoding parallel architectures video coding

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Performance improvement of data mining in Weka through GPU acceleration

Performance improvement of data mining in Weka through GPU a...

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5th international conference on Ambient Systems, Networks and Technologies (ANT) / 4th international conference on Sustainable Energy Information Technology (SEIT)

作者： Engel, Tiago Augusto Charao, Andrea Schwertner Kirsch-Pinheiro, Manuele Steffenel, Luiz-Angelo Univ Fed Santa Maria BR-97119900 Santa Maria RS Brazil Univ Paris 01 F-75231 Paris 05 France Univ Reims Reims France

Data mining tools may be computationally demanding, so there is an increasing interest on parallel computing strategies to improve their performance. the popularization of Graphics processing Units GPUs) increased the computing power of current desktop computers, but desktop-based data mining tools do not usually take full advantage of these architectures. this paper exploits an approach to improve the performance of Weka, a popular data mining tool, through parallelization on GPU-accelerated machines. From the profiling of Weka object-oriented code, we chose to parallelize a matrix multiplication method using state-of-the-art tools. the implementation was merged into Weka so that we could analyze the impact of parallel execution on its performance. the results show a significant speedup on the target parallel architectures, compared to the original, sequential Weka code. (C) 2014 the Authors. Published by Elsevier B.V.

关键词： data mining tools parallel computing GPU

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A low-cost parallel computing platform for power engineering applications

A low-cost parallel computing platform for power engineering...

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5th international conference on Advances in Power Systems Control, Operation and Management

作者： Fung, CC Chow, SY Wong, KP Curtin Univ Technol Sch Elect & Comp Engn Perth WA 6845 Australia

ISBN: (纸本)0852967918

this paper develops and evaluates a low-cost parallel computing platform for the implementation of parallel algorithms in Power Engineering applications. the proposed approach utilises an existing local area network without incurring any additional hardware costs. Application of computational intelligence techniques based on the developed computing platform to the economic dispatch problem is outlined. the performance of genetic algorithms in parallel and cluster structures and their abilities in coping time constraint applications are also demonstrated. It is found that when the workload is large, a parallel computing structure should be exploited for cost-effectiveness purpose.

关键词： parallel processing systems

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Optimal Performance Prediction of ADAS algorithms on Embedded parallel architectures 17

Optimal Performance Prediction of ADAS Algorithms on Embedde...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Saussard, Romain Bouzid, Boubker Vasiliu, Marius Reynaud, Roger Renault SAS Guyancourt France Univ Paris 11 Inst Elect Fondamentale Orsay France

ISBN: (纸本)9781479989379

ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit. Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial. In fact it is not a simple task for automotive industry actors to choose the most suited heterogeneous SoC for a given application. Moreover, embedding complex algorithms on these systems remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on the different computing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processing algorithms applicable on different types of computing units. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms, and a few characteristics of computing units.

关键词： Heterogeneous architectures Embedded Systems Performance Prediction Image processing

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Performance of some image processing algorithms in TensorFlow 25

Performance of some image processing algorithms in TensorFlo...

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25th international conference on Systems, Signals and Image processing (IWSSIP)

作者： Demirovic, Damir Skejic, Emir Serifovic-Trbalic, Amira Univ Tuzla Fac Elect Engn Franjevacka 2 Tuzla 75000 Bosnia & Herceg

ISBN: (纸本)9781538669792

Signal, image and Synthetic Aperture Radar imagery algorithms in recent time are used in a daily routine. Due to huge data and complexity, their processing is almost impossible in a real time. Often image processing algorithms are inherently parallel in nature, so they fit nicely into parallel architectures multicore Central processing Unit (CPU) and Graphics processing Unit GPUs. In this paper image processing algorithms were evaluated, which are capable to execute in parallel manner on several platforms CPU and GPU. All algorithms were tested in TensorFlow, which is a novel framework for deep learning, but also for image processing. Relative speedups compared to CPU were given for all algorithms. TensorFlow GPU implementation can outperform multi-core CPUs for tested algorithms, obtained speedups range from 3.6 to 15 times.

关键词： image processing tensorflow parallel processing central processing unit graphics processing unit

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In-Place Data Sliding algorithms for Many-Core architectures 44

In-Place Data Sliding Algorithms for Many-Core Architectures

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44th Annual international conference on parallel processing Workshops (ICPPW)

作者： Gomez-Luna, Juan Chang, Li-Wen Hwu, Wen-Mei W. Sung, I-Jui Guil, Nicolas Univ Cordoba Comp Architecture & Elect Cordoba Spain Univ Illinois Elect & Comp Engn Urbana IL 61801 USA MulticoreWare Inc Champaign IL USA Univ Malaga Comp Architecture Malaga Spain

ISBN: (纸本)9781467375887

In-place data manipulation is very desirable in many-core architectures with limited on-board memory. this paper deals with the in-place implementation of a class of primitives that perform data movements in one direction. We call these primitives Data Sliding (DS) algorithms. Notable among them are relational algebra primitives (such as select and unique), padding to insert empty elements in a data structure, and stream compaction to reduce memory requirements. their in-place implementation in a bulk synchronous parallel model, such as GPUs, is specially challenging due to the difficulties in synchronizing threads executing on different compute units. Using a novel adjacent work-group synchronization technique, we propose two algorithmic schemes for regular and irregular DS algorithms. With a set of 5 benchmarks, we validate our approaches and compare them to the state-of-the-art implementations of these benchmarks. Our regular DS algorithms demonstrate up to 9.11x and 73.25x on NVIDIA and AMD GPUs, respectively, the throughput of their competitors. Our irregular DS algorithms outperform NVIDIA thrust library by up to 3.24x on the three most recent generations of NVIDIA GPUs.

关键词： in-place stream compaction relational algebra

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