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An optimal parallel prefix-sums algorithm on the memory machine models for GPUs

An optimal parallel prefix-sums algorithm on the memory mach...

引用

12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Nakano, Koji Department of Information Engineering Hiroshima University Kagamiyama 1-4-1 Higashi Hiroshima 739-8527 Japan

ISBN: (纸本)9783642330773

the main contribution of this paper is to show optimal algorithms computing the sum and the prefix-sums on two memory machine models, the Discrete Memory Machine (DMM) and the Unified Memory Machine (UMM). the DMM and the UMM are theoretical parallel computing models that capture the essence of the shared memory and the global memory of GPUs. these models have three parameters, the number p of threads, the width w of the memory, and the memory access latency l. We first show that the sum of n numbers can be computed in time units on the DMM and the UMM. We then go on to show that time units are necessary to compute the sum. Finally, we show an optimal parallel algorithm that computes the prefix-sums of n numbers in time units on the DMM and the UMM. © 2012 Springer-Verlag.

关键词： parallel algorithms

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A Reconfigurable Computing Approach for Efficient and Scalable parallel Graph Exploration

A Reconfigurable Computing Approach for Efficient and Scalab...

引用

23rd IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Betkaoui, Brahim Wang, Yu thomas, David B. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Comp London England Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

ISBN: (纸本)9780769547688

In many application domains, data are represented using large graphs involving millions of vertices and billions of edges. Graph exploration algorithms, such as breadth-first search (BFS), are largely dominated by memory latency and are challenging to process efficiently. In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems. Our methodology is based on a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of the hardware capabilities of both FPGAs and the parallel memory subsystem. To validate our methodology, we provide a detailed design description of the Breadth-First Search algorithm on an FPGA-based high performance computing system. Using graph data based on the power-law graphs found in real-word problems, we are able to achieve performance results that are superior to those of high performance multi-core systems in the recent literature for large graph instances, and a throughput in excess of 2.5 billion traversed edges per second on RMAT graphs with 16 million vertices and over a billion edges. Using four Virtex-5 LX330 FPGAs based on 65nm technology and running at 75MHz, our BFS design achieves more than twice the speed of a 32-core Xeon X7560 based on 45nm technology and running at 2.26GHz.

关键词： Line graph memory latency breadth first search Exploration graph data reconfigurable hardware parallel processing (COMPUTERS) Running Power law

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Design and optimization of high efficiency parallel video coding system

Design and optimization of high efficiency parallel video co...

引用

2012 5th international Joint conference on Computational Sciences and Optimization, CSO 2012

作者： Li, Dongmei Peng, Shuai Li, Zhaohui Information Engineering School Communication University of China Beijing 100024 China

ISBN: (纸本)9780769546902

In order to improve the processing speed of highly complex video coding that involves high data rate and large amount of computation, a parallel video coding system optimization (PVCSO) method is proposed in this paper. By using PC cluster and general H.264 video coding standard for parallel coding experiments, the important factors that are critical to parallel coding efficiency are thoroughly examined and analyzed, such as the number of computation nodes, performance of the network and cluster, parallel coding mechanism, algorithm complexity and raw data distribution mode. Based on the experimental results and analysis, the PVCSO method is proposed and used to design and build practical high efficiency parallel video coding system. For illustration, four high efficiency application-oriented PC cluster based parallel video coding systems are designed and shown. Experimental results show that the PVCSO method can effectively balance the conflicting efficiency factors to achieve the best parallel efficiency and cost performance of the parallel coding system. It provides an effective and practical solution for designing high efficiency parallel video coding system which can significantly improve the processing speed of video coding with huge amount of computation. © 2012 IEEE.

关键词： Computational complexity

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Study of Hierarchical N-Body Methods for Network-on-Chip architectures 1

引用

17th international Euro-Par conference on parallel processing

作者： Xu, thomas Canhao Liljeberg, Pasi Tenhunen, Hannu Turku Ctr Comp Sci Joukahaisenkatu 3-5 B Turku 20520 Finland Univ Turku Dept Informat Technol Turku 20014 Finland

ISBN: (数字)9783642297403

ISBN: (纸本)9783642297403;9783642297397

In this paper, we study two hierarchical N-Body methods for Network-on-Chip (NoC) architectures. the modern Chip Multiprocessor (CMP) designs are mainly based on the shared-bus communication architecture. As the number of cores increases, it suffers from high communication delays. therefore, NoC based architecture is proposed. the N-Body problem is a classical problem of approximating the motion of bodies. Two methods, namely Barnes-Hut (Barnes) and Fast Multipole (FMM), have been developed for fast simulation. the two algorithms have been implemented and studied in conventional computer systems and Graphics processing Units (GPUs). However, as a promising unconventional multicore architecture, the evaluation of N-Body methods in a NoC platform has not been well addressed. We define a NoC model based on state-of-the-art systems. Evaluation results are presented using a cycle accurate full system simulator. Experiments show that, Barnes scales better (53.7x/Barnes and 36.6x/FMM for 64 processing elements) and requires less cache than FMM. However, we observe hot-spot traffic in Barnes. Our analysis and experiment results provide a guideline for studying N-Body methods in a NoC platform.

关键词： Network-on-chip

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Full Custom Datapath of 16-bit CORDIC

Full Custom Datapath of 16-bit CORDIC

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IEEE 5th international conference on Advanced Computational Intelligence (ICACI)

作者： Bi, Zhuo Dai, Yijun Shanghai Univ Sch Mechatron Engn & Automat Shanghai 200041 Peoples R China

ISBN: (纸本)9781467317443

A radix-2 16 bits CORDIC (CoOrdinate Rotation DIgital Computer) architecture which includes pipelined and parallelism is presented in this paper. A full custom technology for CORDIC datapath which is used in the proposed architecture for 16-bit precision can improve the throughout and decrease the area. As a result, the silicon area of the data-path is 11699.877 mu m(2) in the 45nm CMOS technology library and the critical path delay is 875ps at the SS (Slow-Slow) corners whose Voltage and Temperature are 1.1V and 75 degrees C respectively. Based on the layout level, the simulation results show that the design has characteristics of high speed and small area in full custom technology.

关键词： CMOS integrated circuits integrated circuit layout parallel architectures pipeline arithmetic

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HSQL: A highly scalable cloud database for multi-user query processing

HSQL: A highly scalable cloud database for multi-user query ...

引用

2012 IEEE 5th international conference on Cloud Computing, CLOUD 2012

作者： Chang, Chao-Rui Hsieh, Meng-Ju Wu, Jan-Jan Wu, Po-Yen Liu, Pangfeng Institute of Information Science Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan Department of Computer Science and Information Engineering Graduate Institute of Networking and Multimedia National Taiwan University Taipei Taiwan

ISBN: (纸本)9780769547558

With the ever increasing size of data sets, traditional parallel relational database solution can be prohibitively expensive and may suffer limited scalability. To perform large-scale data processing in a cost-effective manner, several NoSQL data processing systems have been proposed. In this paper, we devise a new, distributed B-tree column indexing scheme for HBase, which can support indexing for non-row-key columns, as well as parallel B-tree search in large data table. Our experiment results demonstrate both performance and scalability advantage of our indexing scheme on point queries, range queries, and aggregation operations, compared with HBase. © 2012 IEEE.

关键词： Query processing

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A note on developing optimal and scalable parallel two-list algorithms

A note on developing optimal and scalable parallel two-list ...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Chedid, Fouad B. College of Arts and Applied Sciences Dhofar University Oman Department of Computer Science Notre Dame University - Louaize Lebanon

ISBN: (纸本)9783642330643

We show that developing an optimal parallelization of the two-list algorithm is much easier than we once thought. All it takes is to observe that the steps of the search phase of the two-list algorithm are closely related to the steps of a merge procedure for merging two sorted lists, and we already know how to parallelize merge efficiently. Armed with this observation, we present an optimal and scalable parallel two-list algorithm that is easy to understand and analyze, while it achieves the best known range of processor-time tradeoffs for this problem. In particular, our algorithm based on a CREW PRAM model takes time O(2n/2 - α) using 2α processors, for 0 ≤ α ≤ n/2 - 2logn + 2. © 2012 Springer-Verlag.

关键词： parallel processing systems

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GPU accelerated Wavelet Transform Profilometry

GPU accelerated Wavelet Transform Profilometry

引用

2012 5th international Joint conference on Computational Sciences and Optimization, CSO 2012

作者： Zhou, Bo Zhao, Xiaomin Liu, Chunyuan College of Computer Heilongjiang University of Science and Technology Haerbin 150027 China

ISBN: (纸本)9780769546902

Huge workload and time-consuming of the phase computation based on the Wavelet Transform Profilometry (WTP) so that not meet real-time three-dimensional (3D) measurement needs. Fortunately the pixels which in situ need to be processed and the already processed pixels are independent, so the phase of each pixel can be calculated separately. It is possible to make the phase computation implement on Graphics processing Unit (GPU) with the multi-threading parallel processing, and to solve the problem of the low efficiency on CPU .Experiments show that it obtains the speed up of one to two orders of magnitude to CPU by GPU acceleration with the same accuracy, which lays the solid foundation for WTP applying to the real-time 3D measurement. © 2012 IEEE.

关键词： Graphics processing unit

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parallel algorithm for nonlinear network optimization problems and real-time applications

Parallel algorithm for nonlinear network optimization proble...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Lin, Shin-Yeu Guo, Xian-Chang Department of Electrical Engineering Chang Gung University Tao-Yuan Taiwan

ISBN: (纸本)9783642330773

In this paper, we propose a parallel algorithm to solve a class of nonlinear network optimization problems. the proposed parallel algorithm is a combination of the successive quadratic programming and the dual method, which can achieve complete decomposition and make parallel computation possible. the proposed algorithm can be applied to solve nonlinear network optimization problems in the smart grid. We have tested the proposed parallel algorithm in solving numerous cases of power flow problems on the IEEE 30-bus system. the test results demonstrate that the proposed parallel algorithm can obtain accurate solution. Additionally, neglecting the data communication time, the proposed parallel algorithm is, ideally, 13.1 times faster than the centralized Newton Raphson's method in solving the power flow problems of the IEEE 30-bus system. © 2012 Springer-Verlag.

关键词： parallel algorithms

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Enabling Real-Time Business Intelligence - 5th international Workshop, BIRTE 2011, Held at the 37th international conference on Very Large Databases, VLDB 2011, Revised Selected Papers

Enabling Real-Time Business Intelligence - 5th International...

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5th international Workshop on Enabling Real-Time Business Intelligence, BIRTE 2011, Held at the 37th international conference on Very Large Databases, VLDB 2011

ISBN: (纸本)9783642334993

the proceedings contain 8 papers. the topics discussed include: blink: not your father's database!;MemcacheSQL - a scale-out SQL cache engine;a cost-aware strategy for merging differential stores in column-oriented in-memory DBMS;Microsoft SQL server parallel data warehouse: architecture overview;relax and let the database do the partitioning online;adaptive processing of multi-criteria decision support queries;scalable social graph analytics using the vertica analytic platform;and a near real-time personalization for ecommerce platform.

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