检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,163 篇 会议
71 篇 期刊文献
65 册 图书

馆藏范围

3,298 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

2,338 篇 工学
- 2,058 篇 计算机科学与技术...
- 1,036 篇 软件工程
- 414 篇 电气工程
- 326 篇 信息与通信工程
- 309 篇 电子科学与技术（可...
- 112 篇 控制科学与工程
- 69 篇 机械工程
- 67 篇 光学工程
- 67 篇 生物工程
- 62 篇 生物医学工程（可授...
- 35 篇 动力工程及工程热...
- 33 篇 仪器科学与技术
- 32 篇 建筑学
- 30 篇 材料科学与工程（可...
- 29 篇 化学工程与技术
- 25 篇 土木工程
- 21 篇 力学（可授工学、理...
722 篇 理学
- 483 篇 数学
- 174 篇 物理学
- 80 篇 生物学
- 65 篇 系统科学
- 60 篇 统计学（可授理学、...
- 36 篇 化学
246 篇 管理学
- 158 篇 管理科学与工程(可...
- 102 篇 图书情报与档案管...
- 70 篇 工商管理
62 篇 医学
- 53 篇 临床医学
- 21 篇 基础医学(可授医学...
22 篇 农学
- 19 篇 作物学
21 篇 法学
- 19 篇 社会学
15 篇 经济学
12 篇 文学
11 篇 教育学
4 篇 军事学

主题

327 篇 parallel process...
204 篇 graphics process...
202 篇 computer archite...
156 篇 parallel archite...
136 篇 parallel process...
123 篇 parallel algorit...
121 篇 graphics process...
115 篇 hardware
113 篇 image processing
86 篇 concurrent compu...
86 篇 computational mo...
77 篇 signal processin...
72 篇 parallel program...
72 篇 field programmab...
69 篇 multicore proces...
68 篇 instruction sets
67 篇 parallel computi...
65 篇 algorithm design...
60 篇 gpu
59 篇 throughput

机构

9 篇 college of compu...
9 篇 natl univ def te...
8 篇 carleton univ sc...
8 篇 national laborat...
6 篇 hosei univ dept ...
6 篇 inria rennes
6 篇 st francis xavie...
5 篇 chinese acad sci...
5 篇 univ aizu dept c...
5 篇 polish japanese ...
5 篇 computer science...
5 篇 college of compu...
5 篇 city university ...
4 篇 shanghai jiao to...
4 篇 charles univ pra...
4 篇 rwth aachen univ...
4 篇 hainan internati...
4 篇 department of co...
4 篇 university of ch...
4 篇 universidad carl...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
8 篇 dongarra jack
7 篇 liu jie
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 hannig frank
6 篇 li dongsheng
6 篇 teich juergen
6 篇 li chao
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 krulis martin
5 篇 zhang lei
5 篇 ito yasuaki
5 篇 li kenli
5 篇 wanlei zhou
5 篇 tudruj marek

语言

3,188 篇 英文
99 篇 其他
19 篇 中文

检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3299 条记录，以下是1721-1730 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A note on developing optimal and scalable parallel two-list algorithms

A note on developing optimal and scalable parallel two-list ...

引用

12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Chedid, Fouad B. College of Arts and Applied Sciences Dhofar University Oman Department of Computer Science Notre Dame University - Louaize Lebanon

ISBN: (纸本)9783642330643

We show that developing an optimal parallelization of the two-list algorithm is much easier than we once thought. All it takes is to observe that the steps of the search phase of the two-list algorithm are closely related to the steps of a merge procedure for merging two sorted lists, and we already know how to parallelize merge efficiently. Armed with this observation, we present an optimal and scalable parallel two-list algorithm that is easy to understand and analyze, while it achieves the best known range of processor-time tradeoffs for this problem. In particular, our algorithm based on a CREW PRAM model takes time O(2n/2 - α) using 2α processors, for 0 ≤ α ≤ n/2 - 2logn + 2. © 2012 Springer-Verlag.

关键词： parallel processing systems

来源：评论

学校读者我要写书评

暂无评论

GPU accelerated Wavelet Transform Profilometry

GPU accelerated Wavelet Transform Profilometry

引用

2012 5th international Joint conference on Computational Sciences and Optimization, CSO 2012

作者： Zhou, Bo Zhao, Xiaomin Liu, Chunyuan College of Computer Heilongjiang University of Science and Technology Haerbin 150027 China

ISBN: (纸本)9780769546902

Huge workload and time-consuming of the phase computation based on the Wavelet Transform Profilometry (WTP) so that not meet real-time three-dimensional (3D) measurement needs. Fortunately the pixels which in situ need to be processed and the already processed pixels are independent, so the phase of each pixel can be calculated separately. It is possible to make the phase computation implement on Graphics processing Unit (GPU) with the multi-threading parallel processing, and to solve the problem of the low efficiency on CPU .Experiments show that it obtains the speed up of one to two orders of magnitude to CPU by GPU acceleration with the same accuracy, which lays the solid foundation for WTP applying to the real-time 3D measurement. © 2012 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

parallel algorithm for nonlinear network optimization problems and real-time applications

Parallel algorithm for nonlinear network optimization proble...

引用

12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Lin, Shin-Yeu Guo, Xian-Chang Department of Electrical Engineering Chang Gung University Tao-Yuan Taiwan

ISBN: (纸本)9783642330773

In this paper, we propose a parallel algorithm to solve a class of nonlinear network optimization problems. the proposed parallel algorithm is a combination of the successive quadratic programming and the dual method, which can achieve complete decomposition and make parallel computation possible. the proposed algorithm can be applied to solve nonlinear network optimization problems in the smart grid. We have tested the proposed parallel algorithm in solving numerous cases of power flow problems on the IEEE 30-bus system. the test results demonstrate that the proposed parallel algorithm can obtain accurate solution. Additionally, neglecting the data communication time, the proposed parallel algorithm is, ideally, 13.1 times faster than the centralized Newton Raphson's method in solving the power flow problems of the IEEE 30-bus system. © 2012 Springer-Verlag.

关键词： parallel algorithms

来源：评论

学校读者我要写书评

暂无评论

Enabling Real-Time Business Intelligence - 5th international Workshop, BIRTE 2011, Held at the 37th international conference on Very Large Databases, VLDB 2011, Revised Selected Papers

Enabling Real-Time Business Intelligence - 5th International...

引用

5th international Workshop on Enabling Real-Time Business Intelligence, BIRTE 2011, Held at the 37th international conference on Very Large Databases, VLDB 2011

ISBN: (纸本)9783642334993

the proceedings contain 8 papers. the topics discussed include: blink: not your father's database!;MemcacheSQL - a scale-out SQL cache engine;a cost-aware strategy for merging differential stores in column-oriented in-memory DBMS;Microsoft SQL server parallel data warehouse: architecture overview;relax and let the database do the partitioning online;adaptive processing of multi-criteria decision support queries;scalable social graph analytics using the vertica analytic platform;and a near real-time personalization for ecommerce platform.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Enhancing parallelism of Tile Bidiagonal Transformation on Multicore architectures Using Tree Reduction 1

引用

9th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Ltaief, Hatem Luszczek, Piotr Dongarra, Jack KAUST Supercomputing Laboratory Thuwal Saudi Arabia University of Tennessee Knoxville TN USA Oak Ridge National Laboratory USA University of Manchester United Kingdom

ISBN: (数字)9783642314643

ISBN: (纸本)9783642314636;9783642314643

the objective of this paper is to enhance the parallelism of the tile bidiagonal transformation using tree reduction on multicore architectures. First introduced by Ltaief et. al [LAPACK Working Note # 247, 2011], the bidiagonal transformation using tile algorithms with a two-stage approach has shown very promising results on square matrices. However, for tall and skinny matrices, the inherent problem of processing the panel in a domino- like fashion generates unnecessary sequential tasks. By using tree reduction, the panel is horizontally split, which creates another dimension of parallelism and engenders many concurrent tasks to be dynamically scheduled on the available cores. the results reported in this paper are very encouraging. the new tile bidiagonal transformation, targeting tall and skinny matrices, outperforms the state-of-the-art numerical linear algebra libraries LAPACK V3.2 and Intel MKL ver. 10.3 by up to 29-fold speedup and the standard two-stage PLASMA BRD by up to 20-fold speedup, on an eight socket hexa-core AMD Opteron multicore shared-memory system.

关键词： Bidiagonal Transformation Tree Reduction High Performance Computing Multicore Architecture Dynamic Scheduling

来源：评论

学校读者我要写书评

暂无评论

Design of Unified Support Vector Machine Circuit for Pedestrians and Cars Detection

Design of Unified Support Vector Machine Circuit for Pedestr...

引用

10th IEEE international New Circuits and Systems conference (NEWCAS)

作者： Kim, Soojin Lee, Seonyoung Min, Kyoungwon Cho, Kyeongsoon Hankuk Univ Foreign Studies Dept Elect & Informat Engn Yongin South Korea Korea Elect Technol Inst SoC Platform Res Ctr Sungnam South Korea

ISBN: (纸本)9781467308595

this paper describes the design of unified support vector machine circuit for pedestrians and cars detection. By unifying the algorithms and architectures of linear and nonlinear SVM classifications, the proposed circuit can support both linear and non-linear classifications very efficiently in terms of circuit size and performance. the circuit size is minimized by sharing most of the resources required in the computation for both classification types. parallel architecture with pipeline is adopted to accelerate the processing speed to handle a large amount of operations for real-time processing. 48x96 and 64x64 sliding windows with 6 window strides are used to detect pedestrians and cars, respectively. the synthesized circuit using 65nm standard cell library consists of 848,349 gates and its maximum operating frequency is 435MHz. the circuit can process 91.9 640x480 image frames per second assuming three cameras equipped on front, right and left side positions of the vehicle.

关键词： Pedestrians Cars Support Vector Network maximum operating frequency ARCHITECTURE processing SPEED Building construction pipeline Linear

来源：评论

学校读者我要写书评

暂无评论

A verified library of algorithmic skeletons on evenly distributed arrays

A verified library of algorithmic skeletons on evenly distri...

引用

12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Bousdira, Wadoud Loulergue, Frédéric Tesson, Julien LIFO University of Orléans France Kochi University of Technology Japan

ISBN: (纸本)9783642330773

To make parallel programming as widespread as parallel architectures, more structured parallel programming paradigms are necessary. One of the possible approaches are algorithmic skeletons. they can be seen as higher order functions implemented in parallel. Algorithmic skeletons offer a simple interface to the programmer without all the details of parallel implementations as they abstract the communications and the synchronisations of parallel activities. To write a parallel program, users have to combine and compose the skeletons. Orléans Skeleton Library (OSL) is an efficient meta-programmed C++ library of algorithmic skeletons that manipulate distributed arrays. A prototype implementation of OSL exists as a library written with the function parallel language Bulk Synchronous parallel ML (BSML). In this paper we are interested in verifying the correctness of a subset of this prototype implementation. To do so, we give a functional specification of a subset of OSL and we prove the correctness of the BSML implementation with respect to this functional specification, using the Coq proof assistant. To illustrate how the user could use these skeletons, we prove the correctness of two applications implemented with them. © 2012 Springer-Verlag.

关键词： parallel programming

来源：评论

学校读者我要写书评

暂无评论

Energy efficient high-performance computing using ARM Cortex-A9 cores

Energy efficient high-performance computing using ARM Cortex...

引用

IEEE/ACM international conference on Green Computing and Communications (GreenCom) / IEEE international conference on Internet of things (ithings) / 5th IEEE international conference on Cyber, Physical and Social Computing (CPSCom)

作者： Pleiter, D. Richter, M. Forschungszentrum Julich Julich Supercomp Ctr D-52425 Julich Germany

ISBN: (纸本)9780769548654;9781467351461

In this paper we investigate the energy efficiency of processors based on ARM Cortex-A9 cores for scientific numerical applications. We study the performance for a few numerical kernels which appear in a larger set of scientific applications. From power measurements that were performed on different platforms we estimate the energy consumed when executing these kernels.

关键词： energy conservation parallel processing

来源：评论

学校读者我要写书评

暂无评论

An Efficient High Performance parallel Algorithm to Yield Reduced Wire Length VLSI Circuits

An Efficient High Performance Parallel Algorithm to Yield Re...

引用

5th international conference on Computers and Devices for Communication (CODEC)

作者： Sau, Swagata Saha Pal, Rajat Kumar Sammilani Mahavidyalaya Dept Comp Sci Kolkata India Univ Calcutta Dept Comp Sci & Engn Kolkata India

ISBN: (纸本)9781467326209;9781467326193

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment. In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit. thus it has a direct impact on daily life and environment. Channel routing problem for wire length minimization is an NP-hard problem. Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length. In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model. the performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels.

关键词： Channel routing problem wire length minimization TAH framework parametric difference parallel processing

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of High speed VLSI architectures for AES Algorithm

FPGA Implementation of High speed VLSI Architectures for AES...

引用

5th international conference on Emerging Trends in Engineering and Technology (ICETET)

作者： Kshirsagar, R. V. Vyawahare, M. V. Priyadarshini Coll Engn Elect Engn Deptt Nagpur Maharashtra India

ISBN: (纸本)9780769548845;9781479902767

In this paper, we have proposed high data throughput AES hardware architecture by partitioning ten rounds into sub-blocks of repeated AES modules. the blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. In addition, the AES is internally evenly divided to ten pipeline stages;with the additional feature that the shift rows block (Shift Row) is structured to operate before the byte substitute (Byte Substitute) block. this proposed swapping operation has no effect on the AES encryption algorithm;however, it streamlines the processing of four blocks of data in parallel rather than 16 blocks, which is considered as the key advantage for area saving. We have evaluated the performance of our implementation in terms of throughput rate and hardware area for Xilinx's SPARTAN-3 FPGA. the simulation results show that the proposed AES has higher throughput rate of about 4.25% than the general AES pipeline structure with a saving hardware area of 56%.

关键词： AES pipeline FPGA GF ((2(4))(2)) Rijndael S-BOX

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共330页 << < 169 170 171 172 173 174 175 176 177 178 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：