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Performance evaluation of OpenMP and CUDA on multicore systems

Performance evaluation of OpenMP and CUDA on multicore syste...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Yang, Chao-Tung Chang, Tzu-Chieh Huang, Kuan-Lung Liu, Jung-Chun Chang, Chih-Hung Department of Computer Science Tunghai University Taichung City 40704 Taiwan Department of Information Management Hsiuping University of Science Technology Taichung City 41280 Taiwan

ISBN: (纸本)9783642330643

Nowadays, not only CPU but also GPU goes along the trend of multi-core processors. parallel processing presents not only an opportunity but also a challenge at the same time. To explicitly parallelize the software by programmers or compilers is the key for enhancing the performance on multi-core chip. In this paper, we first introduce some of the automatic parallel tools based OpenMP, which could save the time to rewrite codes for parallel processing on multicore system. then we focus on ROSE and explore it in depth. And we also implement an interface to reduce its complexity of use and use some automatic parallelization for CUDA. © 2012 Springer-Verlag.

关键词： parallel programming

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Performance measurement of parallel Vlasov code for space plasma on various scalar-type supercomputer systems

Performance measurement of parallel Vlasov code for space pl...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Umeda, Takayuki Fukazawa, Keiichiro Solar-Terrestrial Environment Laboratory Nagoya University Nagoya 464-8601 Japan Research Institute for Information Technology Kyushu University Fukuoka 812-8581 Japan

ISBN: (纸本)9783642330773

Computer simulations with the first-principle (kinetic) model are essential for studying multi-scale processes in space plasma. We develop numerical schemes for Vlasov simulations for practical use on currently-existing supercomputer systems. the weak-scaling benchmark test shows that our parallel Vlasov code achieves a high performance and a high scalability. Currently, we use more than 1000 cores for parallel computations and apply the present parallel Vlasov code to various cross-scale processes in space plasma, such as a first-principle global simulation of solar-wind-magnetosphere interactions. © 2012 Springer-Verlag.

关键词： Supercomputers

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An implementation of parallel 2-D FFT using intel AVX instructions on multi-core processors

An implementation of parallel 2-D FFT using intel AVX instru...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Takahashi, Daisuke Faculty of Engineering Information and Systems University of Tsukuba 1-1-1 Tennodai Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9783642330643

In this paper, we propose an implementation of a parallel two-dimensional fast Fourier transform (FFT) using Intel Advanced Vector Extensions (AVX) instructions on multi-core processors. the combination of vectorization and a block two-dimensional FFT algorithm is shown to effectively improve performance. We vectorized FFT kernels using the AVX instructions. Performance results of two-dimensional FFTs on multi-core processors are reported. We successfully achieved a performance of over 61 GFlops on an Intel Xeon E5-2670 (2.6 GHz, two CPUs, 16 cores) and over 24 GFlops on an Intel Core i7-3930K (3.2 GHz, one CPU, six cores) for a 212 x 212-point FFT. © 2012 Springer-Verlag.

关键词： Fast Fourier transforms

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A new low latency parallel turbo decoder employing parallel phase decoding method

A new low latency parallel turbo decoder employing parallel ...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

作者： Lee, Wen-Ta Chang, Min-Sheng Shen, Wei-Chieh Institute of Computer and Communication National Taipei University of Technology Taipei Taiwan

ISBN: (纸本)9783642330643

In this paper, a new parallel phase algorithm for parallel turbo decoder is proposed. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce long decoding latency. the proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. For verifying the proposed parallel phase turbo decoder, we have used FPGA to emulate the hardware architectures, and designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. the gate count of this decoder chip is 128284. the chip size including I/O pad is 1.91x1.91mm2. the simulation result shows that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.23%~58.13% decoding time saved, with 8 iteration times at 100MHz working frequency. © 2012 Springer-Verlag.

关键词： Iterative decoding

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the Design and Implementation of a Multi-level Content-Addressable Checkpoint File System

The Design and Implementation of a Multi-level Content-Addre...

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19th international conference on High Performance Computing (HiPC)

作者： Kulkarni, Abhishek Manzanares, Adam Ionkov, Latchesar Lang, Michael Lumsdaine, Andrew Indiana Univ Bloomington IN 47405 USA Los Alamos Natl Lab Los Alamos NM USA

ISBN: (纸本)9781467323703;9781467323727

Long-running HPC applications guard against node failures by writing checkpoints to parallel file systems. Writing these checkpoints with petascale class machines has proven difficult and the increased concurrency demands of exascale computing will exacerbate this problem. To meet checkpointing demands and sustain application-perceived throughput at exascale, multi-tiered hierarchical storage architectures involving solid-state burst buffers are being considered. In this paper, we describe the design and implementation of cento, a multi-level, content-addressable checkpoint file system for large-scale HPC systems. cento achieves in-flight checkpoint data reduction across all compute nodes through compression and elimination of duplicate blocks over a series of checkpoints. through a detailed analysis of checkpoint dumps, we assess the benefits of data reduction for scientific applications that are representative of production workloads. We observe upto 40% data reduction within a limited sample of representative workloads. Finally, experiments on existing systems show a decrease in checkpoint commit latencies by 5 to 20% reducing the load on the parallel file system.

关键词： checkpointing concurrency control content-addressable storage data compression data reduction parallel processing

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Scheduling parallel machines with a single server: A dedicated case

Scheduling parallel machines with a single server: A dedicat...

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2012 5th international Joint conference on Computational Sciences and Optimization, CSO 2012

作者： Xie, Xie Zheng, Yongyue Li, Yanping Key Laboratory of Manufacturing Industrial and Integrated Automation Shenyang University Shenyang 110044 China Liaoning Institute of Standardization Shenyang 110004 China

ISBN: (纸本)9780769546902

the model in this paper is abstracted from a key course of batch annealing process in the steel industry: heating or cooling. We mainly investigate scheduling parallel dedicated machines with a single sever as well as additional constraints on setups and removals. It generalizes classical parallel machine scheduling problem with a single server which needs to perform setup operation of each job only. the single server in our problem do not only load a job on a machine which takes a certain setup time immediately before processing but also unload a job from the machine which takes a certain removal time after processing. the objective is to minimize makespan. A polynomial time approximate algorithm is proposed with a tight worst-case bound at most twice as large as the optimal value. © 2012 IEEE.

关键词： Computational complexity

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Research of parallel Data processing, Anti-light Interference Infrared Touch Technology

Research of Parallel Data Processing, Anti-light Interferenc...

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IEEE 5th international conference on Advanced Computational Intelligence (ICACI)

作者： Li, Yi Huang, Ziqiang Li, Guoying Univ Elect Sci & Technol China Res Inst Elect Sci & Technol Chengdu Sichuan Peoples R China Sch Beijing Aeronaut Technol Res Ctr Beijing Peoples R China

ISBN: (纸本)9781467317443

Large-size infrared touch screen has long response time and external light interference problems. To solve these problems, this paper proposes a method that divides whole infrared touch screen into several separate scanning units and a master module. Each scanning unit completes touch scanning and touch information processing within its own range. Scanning units are parallel working. Master module gets touch information from each scanning unit through UART bus, processes touch information to get final touch coordinates of the whole screen and reports them to host computer. through parallel working among scanning-units rather than sequential scanning on full-screen, this method improves the response speed. through using photodiode and crystal resonator to constitute received signal processing circuit, this method achieves anti-light interference. After response time tested and anti-light interference tested, it has proved that this method achieves a fast response and anti-light interference infrared touch screen system.

关键词： photodiodes touch sensitive screens

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Password Recovery Using MPI and CUDA

Password Recovery Using MPI and CUDA

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19th international conference on High Performance Computing (HiPC)

作者： Apostal, David Foerster, Kyle Chatterjee, Amrita Desell, Travis Univ North Dakota Dept Comp Sci Grand Forks ND 58201 USA Univ North Dakota Dept Elect Engn Grand Forks ND USA

ISBN: (纸本)9781467323703;9781467323727

Using passwords to verify a user's identity is the most widely deployed method for electronic authentication. When system administrators need to recover lost passwords or test accounts for easily guessable passwords, it can require millions of hash function and string comparison operations. these operations can be computationally expensive but are easily parallelizable because each password can be tested independently. therefore, using high performance computing (HPC) can greatly reduce the time required to perform password recovery. Due to the high level of fine-grained parallelism of this type of problem, GPU computing using Compute Unified Device Architecture (CUDA) can be used to further improve performance. the scale of HPC can be further increased through the use of multiple GPUs, but this requires communication between the GPU devices and can reduce the overall performance due to increased communications latency. In this work a well established HPC framework, Message Passing Interface (MPI), was used to minimize the amount of latency and handle the communication between the devices. this allowed for a course-grained division of the problem using MPI where each device applies a fine-grained division of the problem using CUDA to perform the actual calculations. this paper describes three dictionary-based password recovery algorithms that use both MPI and CUDA. In this approach the hashed values of known words are computed and compared with hash values of unknown user passwords. the algorithms differed in GPU memory utilization and how the data was divided and distributed among the MPI nodes and GPU devices. A divided dictionary algorithm split the dictionary of potential passwords over the GPUs and copied the password database to each GPU. A divided password database algorithm split the password database and copied the potential passwords. A minimal memory algorithm split the password database and sequentially processed individual passwords on the GPUs. the div

关键词： application program interfaces database management systems graphics processing units message passing parallel architectures security of data storage management

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Introducing 'bones': A parallelizing source-to-source compiler based on algorithmic skeletons 5

Introducing 'bones': A parallelizing source-to-source compil...

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5th Workshop on General-Purpose Computation on Graphics processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Nugteren, Cedric Corporaal, Henk Eindhoven University of Technology Netherlands

ISBN: (纸本)9781450312332

Recent advances in multi-core and many-core processors requires programmers to exploit an increasing amount of parallelism from their applications. Data parallel languages such as CUDA and OpenCL make it possible to take advantage of such processors, but still require a large amount of effort from programmers. A number of parallelizing source-to-source compilers have recently been developed to ease programming of multi-core and many-core processors. this work presents and evaluates a number of such tools, focused in particular on C-to-CUDA transformations targeting GPUs. We compare these tools both qualitatively and quantitatively to each other and identify their strengths and weaknesses. In this paper, we address the weaknesses by presenting a new classification of algorithms. this classification is used in a new source-to-source compiler, which is based on the algorithmic skeletons technique. the compiler generates target code based on skeletons of parallel structures, which can be seen as parameterisable library implementations for a set of algorithm classes. We furthermore demonstrate that the presented compiler requires little modifications to the original sequential source code, generates readable code for further fine-tuning, and delivers superior performance compared to other tools for a set of 8 image processing kernels. © 2012 ACM.

关键词： parallel programming

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Artificial General Intelligence - 5th international conference, AGI 2012, Proceedings

Artificial General Intelligence - 5th International Conferen...

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5th international conference on Artificial General Intelligence, AGI 2012

ISBN: (纸本)9783642355059

the proceedings contain 38 papers. the topics discussed include: creativity, cognitive mechanisms, and logic;MicroPsi 2: the next generation of the MicroPsi framework;an extensible language interface for robot manipulation;noisy reasoners: errors of judgement in humans and AIs;a representation theorem for decisions about causal models;modular value iteration through regional decomposition;perception processing for general intelligence: bridging the symbolic/subsymbolic gap;on attention mechanisms for AGI architectures: a design proposal;a framework for representing action meaning in artificial systems via force dimensions;avoiding unintended AI behaviors;decision support for safe AI design;on measuring social intelligence: experiments on competition and cooperation;and toward tractable AGI: challenges for system identification in neural circuitry.

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