检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,157 篇 会议
72 篇 期刊文献
65 册 图书

馆藏范围

3,293 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

2,338 篇 工学
- 2,058 篇 计算机科学与技术...
- 1,036 篇 软件工程
- 414 篇 电气工程
- 326 篇 信息与通信工程
- 310 篇 电子科学与技术（可...
- 112 篇 控制科学与工程
- 69 篇 机械工程
- 67 篇 光学工程
- 67 篇 生物工程
- 62 篇 生物医学工程（可授...
- 35 篇 动力工程及工程热...
- 33 篇 仪器科学与技术
- 32 篇 建筑学
- 30 篇 材料科学与工程（可...
- 29 篇 化学工程与技术
- 25 篇 土木工程
- 21 篇 力学（可授工学、理...
721 篇 理学
- 482 篇 数学
- 174 篇 物理学
- 79 篇 生物学
- 65 篇 系统科学
- 60 篇 统计学（可授理学、...
- 36 篇 化学
246 篇 管理学
- 158 篇 管理科学与工程(可...
- 102 篇 图书情报与档案管...
- 70 篇 工商管理
63 篇 医学
- 53 篇 临床医学
- 21 篇 基础医学(可授医学...
22 篇 农学
- 19 篇 作物学
21 篇 法学
- 19 篇 社会学
15 篇 经济学
12 篇 文学
11 篇 教育学
4 篇 军事学

主题

327 篇 parallel process...
204 篇 graphics process...
203 篇 computer archite...
157 篇 parallel archite...
136 篇 parallel process...
123 篇 parallel algorit...
121 篇 graphics process...
115 篇 hardware
113 篇 image processing
86 篇 concurrent compu...
86 篇 computational mo...
76 篇 signal processin...
72 篇 parallel program...
71 篇 field programmab...
68 篇 instruction sets
68 篇 multicore proces...
67 篇 parallel computi...
65 篇 algorithm design...
58 篇 throughput
57 篇 gpu

机构

9 篇 college of compu...
9 篇 natl univ def te...
8 篇 carleton univ sc...
8 篇 national laborat...
6 篇 hosei univ dept ...
6 篇 inria rennes
6 篇 st francis xavie...
5 篇 chinese acad sci...
5 篇 univ aizu dept c...
5 篇 polish japanese ...
5 篇 computer science...
5 篇 college of compu...
5 篇 city university ...
4 篇 shanghai jiao to...
4 篇 charles univ pra...
4 篇 rwth aachen univ...
4 篇 hainan internati...
4 篇 department of co...
4 篇 university of ch...
4 篇 universidad carl...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
8 篇 dongarra jack
7 篇 liu jie
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 hannig frank
6 篇 li dongsheng
6 篇 teich juergen
6 篇 li chao
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 krulis martin
5 篇 zhang lei
5 篇 ito yasuaki
5 篇 li kenli
5 篇 wanlei zhou
5 篇 tudruj marek

语言

3,230 篇 英文
53 篇 其他
15 篇 中文

检索条件"任意字段=5th International Conference on Algorithms and Architectures for Parallel Processing"

共 3294 条记录，以下是1781-1790 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Solving Sudoku in reconfigurable hardware

Solving Sudoku in reconfigurable hardware

引用

international conference on Computing and Networking Technology (ICCNT)

作者： Iouliia Skliarova Tiago Vallejo Valery Sklyarov IEETA Department of Electronics Telecommunications and Informatics University of Aveiro Aveiro Portugal

In this paper we explore the effectiveness of solution of computationally intensive problems in FPGA (Field-Programmable Gate Array) on an example of Sudoku game. three different Sudoku solvers have been fully implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family. the first solver is only able to deal with simple puzzles with reasoning, i.e. without search. the second solver applies breadth-first search algorithm and therefore has virtually no limitation on the type of puzzles which are solvable. We prove that despite the serial nature of implemented backtracking search algorithms, parallelism can be used efficiently. thus, the suggested third solver explores the possibility of parallel processing of search tree branches and boosts the performance of the second solver. the trade-offs of the designed solvers are analyzed, the results are compared to software and to other known implementations, and conclusions are drawn on how to improve the suggested architectures.

关键词： Field programmable gate arrays Engines Software Computer architecture Software algorithms parallel processing Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

Bio-inspired transputer based-fuzzy mobile robot

Bio-inspired transputer based-fuzzy mobile robot

引用

5th international ICST conference on Bio-Inspired Models of Network, Information, and Computing Systems, BIONETICS 2010

作者： Mattar, Ebrahim Al-Mutib, Khalid Hamdan, Hani Hamdan, Mohamad University of Bahrain P.O. Box 32038 Bahrain King Saud University College of Computer and Information Sciences Department of Software Engineering P.O. Box 51178 Saudi Arabia SUPELEC Department of Signal Processing and Electronic Systems Rue Joliot-Curie 91192 Gif-sur-Yvette Cedex France Université Libanaise Faculté de Génie Department of Electrical and Electronics Engineering Beirut Lebanon

ISBN: (纸本)9783642326141

Mobile robots have been used widely in large number of intelligent based applications, where a random manoeuvring is an essential part of such systems, [1,2]. In this regards, experience has shown that mobile robots do require advanced parallel intelligent based control mechanisms. In this article, it is shown how a mobile robot can be controlled in movement via some rule based system. In this sense, the design, construction and testing of an autonomous mobile robot have already been defined in the literature. A Transputer Embedded Real-Time Controller has been widely used for industrial applications due to their advances. Here, a Fuzzy based Transputer System is used (on board the robot) to meet some intelligence requirements for the navigation and obstacle avoidance. A parallel fuzzy controller is implemented for a mobile robot guidance and obstacle avoidance. this is based on parallel processing of sonar data that do come from the mobile sensory system. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.

关键词： Mobile robots

来源：评论

学校读者我要写书评

暂无评论

Optimizing Option Pricing algorithms and Profiling Power Consumption on VLIW APU Architecture

Optimizing Option Pricing Algorithms and Profiling Power Con...

引用

international Symposium on parallel and Distributed processing with Applications, ISPA

作者： Matthew Doerksen Parimala thulasiraman Ruppa K. thulasiram Department of Computer Science University of Manitoba Winnipeg MAN Canada

Heterogeneous multi-core architectures have become an integral component of high performance systems and high performance scientific computing (HPC). the use of these systems has been vital for research applications but until recently have not been a factor in the consumer level experience. However, with new technologies such as AMD's Accelerated processing Unit (APU) which combines the Central processing Unit and Graphics processing Unit onto a single die, consumers now have an affordable high performance system at their disposal. AMD's APUs are aimed at providing good performance and low power consumption for all markets. Financial applications can benefit from this heterogeneous architecture for real time processing. However, to obtain good performance, algorithms must be coded to efficiently utilize the APU architecture. In this paper, we have optimized two option pricing algorithms on the APU making use of vectorization and loop unrolling for improved performance. Our algorithms are tested on both an ATI Mobility Radeon 5870 and an AMD E-350 APU which use the VLIW5 architecture. We also study the power consumption of these architectures to determine how they compare to traditional CPU- and GPU- based systems.

关键词： Lattices Pricing Computer architecture Graphics processing unit Power demand Instruction sets Europe

来源：评论

学校读者我要写书评

暂无评论

Enabling task-level scheduling on heterogeneous platforms 5

Enabling task-level scheduling on heterogeneous platforms

引用

5th Workshop on General-Purpose Computation on Graphics processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Sun, Enqiang Schaa, Dana Bagley, Richard Rubin, Norman Kaeli, David Department of Electrical and Computer Engineering Northeastern University Boston MA United States Graphics Product Group Advanced Micro Devices Boxborough MA United States

ISBN: (纸本)9781450312332

OpenCL is an industry standard for parallel programming on heterogeneous devices. With OpenCL, compute-intensive portions of an application can be offloaded to a variety of processing units within a system. OpenCL is the first standard that focuses on portability, allowing programs to be written once and run seamlessly on multiple, heterogeneous devices, regardless of vendor. While OpenCL has been widely adopted, there still remains a lack of support for automatic task scheduling and data consistency when multiple devices appear in the system. To address this need, we have designed a task queueing extension for OpenCL that provides a high-level, unified execution model tightly coupled with a resource management facility. the main motivation for developing this extension is to provide OpenCL programmers with a convenient programming paradigm to fully utilize all possible devices in a system and incorporate flexible scheduling schemes. To demonstrate the value and utility of this extension, we have utilized an advanced OpenCL-based imaging toolkit called clSURF. Using our task queueing extension, we demonstrate the potential performance opportunities and limitations given current vendor implementations of OpenCL. Using a state-of-art implementation on a single GPU device as the baseline, our task queueing extension achieves a speedup up to 72.4%. Our extension also achieves scalable performance gains on multiple heterogeneous GPU devices. the performance trade-offs of using the host CPU as an accelerator are also evaluated. © 2012 ACM.

关键词： parallel programming

来源：评论

学校读者我要写书评

暂无评论

Paragon: Collaborative speculative loop execution on GPU and CPU 5

Paragon: Collaborative speculative loop execution on GPU and...

引用

5th Workshop on General-Purpose Computation on Graphics processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Samadi, Mehrzad Hormati, Amir Lee, Janghaeng Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States Microsoft Research Microsoft Inc. Redmond WA United States

ISBN: (纸本)9781450312332

the rise of graphics engines as one of the main parallel platforms for general purpose computing has ignited a wide search for better programming support for GPUs. Due to their non-traditional execution model, developing applications for GPUs is usually very challenging, and as a result, these devices are left under-utilized in many commodity systems. Several languages, such as CUDA, have emerged to solve this challenge, but past research has shown that developing applications in these languages is a daunting task because of the tedious performance optimization cycle or inherent algorithmic characteristics of an application, which could make it unsuitable for GPUs. Also, previous approaches of automatically generating optimized parallel code in CUDA for GPUs using complex compilation techniques have failed to utilize GPUs that are present in everyday computing devices such as laptops and mobile systems. In this work, we take a different approach. Although it is hard to generate optimized code for GPU, it is beneficial to utilize them speculatively rather than leaving them running idle due to their high raw performance capabilities compared to CPUs. To achieve this goal, we propose Paragon: a collaborative static/dynamic compiler platform to speculatively run possibly-data-parallel pieces of sequential applications on GPUs. Paragon utilizes the GPU in an opportunistic way for loops that are categorized as possibly-data-parallel by its loop classification phase. While running the loop speculatively, Paragon monitors the dependencies using a light-weight kernel management unit, and transfers the execution to the CPU in case a conflict is detected. Paragon resumes the execution on the GPU after the dependency is executed sequentially on the CPU. Our experiments show that Paragon achieves up to 12x speedup compared to unsafe CPU execution with 4 threads. © 2012 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Porting a H264/AVC adaptive in loop deblocking filter to a TI DM6437EVM DSP

Porting a H264/AVC adaptive in loop deblocking filter to a T...

引用

5th international conference on Image and Signal processing, ICISP 2012

作者： Skoudarli, Abdellah Nibouche, Mokhtar Serir, Amina USTHB Faculty of Electronic and Informatic Laboratory of Image Processing and Radiation BP 32 El Alia Bab Ezzouar Alger Algeria Frenchay Campus UWE Coldharbour Lane Bristol BS16 1QY United Kingdom

ISBN: (纸本)9783642312533

Complementary units in the form encoders and decoders are generally involved in video compression standards. Both the encoder and the decoder integrate an adaptive deblocking filter, which is very beneficial in preserving and enhancing the video quality. Deblocking filters are extremely popular in improving the visual quality of decoded frames in the H.264/AVC video coding standard. the prime goal of the current paper is to efficiently implement a H.264/AVC adaptive deblocking filter using the Texas Instruments DM6437EVM DSP processor. the adopted approach requires an initial identification of the portions of the algorithm wherein parallel processing can be exploited. the functions are then re-written and the instructions rearranged using the features of the targeted hardware architecture. the adaptive deblocking algorithm was optimised and ported to a DM6437EVM DSP platform. A quick comparison shows that the optimised code is a 32 % better, in terms of speed, than the non-optimised code. © 2012 Springer-Verlag.

关键词： Video signal processing

来源：评论

学校读者我要写书评

暂无评论

An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

An efficient high performance parallel algorithm to yield re...

引用

international conference on Computers and Devices for Communication (CODEC)

作者： Swagata Saha Sau Rajat Kumar Pal Department of Computer Science Sammilani Mahavidyalaya Kolkata India Department of Computer Science and Engineering University of Calcutta Kolkata India

ISBN: (纸本)9781467326193

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment. In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit. thus it has a direct impact on daily life and environment. Channel routing problem for wire length minimization is an NP-hard problem. Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length. In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model. the performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels.

关键词： Channel routing problem wire length minimization TAH framework parametric difference parallel processing Wire length parallel processing (COMPUTERS) Very large scale integration parallel algorithms channel routing ELECTRICAL HAZARDS Green technology used area

来源：评论

学校读者我要写书评

暂无评论

GPUstore: Harnessing GPU computing for storage systems in the OS kernel 12

GPUstore: Harnessing GPU computing for storage systems in th...

引用

5th Annual international Systems and Storage conference, SYSTOR 2012

作者： Sun, Weibin Ricci, Robert Curry, Matthew L. University of Utah United States Sandia National Laboratories United States

ISBN: (纸本)9781450314480

Many storage systems include computationally expensive components. Examples include encryption for confidentiality, checksums for integrity, and error correcting codes for reliability. As storage systems become larger, faster, and serve more clients, the demands placed on their computational components increase and they can become performance bottlenecks. Many of these computational tasks are inherently parallel: they can be run independently for different blocks, files, or I/O requests. this makes them a good fit for GPUs, a class of processor designed specifically for high degrees of parallelism: consumer-grade GPUs have hundreds of cores and are capable of running hundreds of thousands of concurrent threads. However, because the software frameworks built for GPUs have been designed primarily for the long-running, data-intensive workloads seen in graphics or high-performance computing, they are not well-suited to the needs of storage systems. In this paper, we present GPUstore, a framework for integrating GPU computing into storage systems. GPUstore is designed to match the programming models already used these systems. We have prototyped GPUstore in the Linux kernel and demonstrate its use in three storage subsystems: file-level encryption, block-level encryption, and RAID 6 data recovery. Comparing our GPU-accelerated drivers with the mature CPU-based implementations in the Linux kernel, we show performance improvements of up to an order of magnitude. © 2012 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Scalable Distributed Fast Multipole Methods

Scalable Distributed Fast Multipole Methods

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Qi Hu Nail A. Gumerov Ramani Duraiswami University of Maryland Institute for Advanced Computer Studies (UMIACS) USA

the Fast Multipole Method (FMM) allows O(N) evaluation to any arbitrary precision of N-body interactions that arises in many scientific contexts. these methods have been parallelized, with a recent set of papers attempting to parallelize them on heterogeneous CPU/GPU architectures [1]. While impressive performance was reported, the algorithms did not demonstrate complete weak or strong scalability. Further, the algorithms were not demonstrated on nonuniform distributions of particles that arise in practice. In this paper, we develop an efficient scalable version of the FMM that can be scaled well on many heterogeneous nodes for nonuniform data. Key contributions of our work are data structures that allow uniform work distribution over multiple computing nodes, and that minimize the communication cost. these new data structures are computed using a parallel algorithm, and only require a small additional computation overhead. Numerical simulations on a heterogeneous cluster empirically demonstrate the performance of our algorithm.

关键词： Receivers Partitioning algorithms Octrees Graphics processing unit Vegetation Clustering algorithms

来源：评论

学校读者我要写书评

暂无评论

REAL-TIME BLOCK MATCHING MOTION ESTIMATION ONTO GPGPU

REAL-TIME BLOCK MATCHING MOTION ESTIMATION ONTO GPGPU

引用

IEEE international conference on Image processing

作者： Eduarda Monteiro Marilena Maule Felipe Sampaio Claudio Diniz Bruno Zatt Sergio Bampi Informatics Institute-PPGC-PGMICRO Federal University of Rio Grande do Sul Porto Alegre Brazil

this work presents an efficient method to map Motion Estimation (ME) algorithms onto General Purpose Graphic processing Unit (GPGPU) architectures using CUDA programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelization potential of ME algorithms: Full Search (FS) and Diamond Search (DS). Our main goal is to evaluate the feasibility of achieving real-time high-definition video encoding performance running on GPUs. For comparison reasons, multi-core parallel and distributed versions of these algorithms were developed using OpenMP and MPI (Message Passing Interface) libraries, respectively. the CUDA-based solutions achieve the highest speed-up in comparison with OpenMP and MPI versions for both algorithms and, when compared to the state-of-the-art, our FS and DS solutions reach up to 18x and 11x speed-up, respectively.

关键词： Graphics processing units Motion estimation Algorithm design and analysis Computer architecture Real-time systems Diamonds Programming

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共330页 << < 175 176 177 178 179 180 181 182 183 184 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：