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An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits

An efficient high performance parallel algorithm to yield re...

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international conference on Computers and Devices for Communication (CODEC)

作者： Swagata Saha Sau Rajat Kumar Pal Department of Computer Science Sammilani Mahavidyalaya Kolkata India Department of Computer Science and Engineering University of Calcutta Kolkata India

ISBN: (纸本)9781467326193

Green technology is a new research area in electronics, which meets the needs of society and explores the ability of VLSI circuits and embedded systems to positively impact the environment. In VLSI physical design automation, channel routing is a fundamental problem but reducing the total wire length for interconnecting the nets of different circuit blocks is one of the most challenging requirements to enhance the performance of a chip to be designed. Reducing the total wire length for interconnection not only minimizes the cost of the physical wire segments required, but also reduces the amount of occupied area for interconnection, signal propagation delays, electrical hazards, power consumption, heat generation, and over all the parasitics present in a circuit. thus it has a direct impact on daily life and environment. Channel routing problem for wire length minimization is an NP-hard problem. Hence as a part of developing an alternative, we modify the existing graph theoretic framework Track_Assignment_Heuristic (TAH) to reduce the total (vertical) wire length. In this paper we propose an efficient polynomial time graph based parallel algorithm to reduce the total wire length without radically increasing of required area for interconnection in the reserved two-layer no-dogleg Manhattan channel routing model. the performance and efficiency of our algorithm is highly encouraging for different well-known benchmarks channels.

关键词： Channel routing problem wire length minimization TAH framework parametric difference parallel processing Wire length parallel processing (COMPUTERS) Very large scale integration parallel algorithms channel routing ELECTRICAL HAZARDS Green technology used area

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GPUstore: Harnessing GPU computing for storage systems in the OS kernel 12

GPUstore: Harnessing GPU computing for storage systems in th...

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5th Annual international Systems and Storage conference, SYSTOR 2012

作者： Sun, Weibin Ricci, Robert Curry, Matthew L. University of Utah United States Sandia National Laboratories United States

ISBN: (纸本)9781450314480

Many storage systems include computationally expensive components. Examples include encryption for confidentiality, checksums for integrity, and error correcting codes for reliability. As storage systems become larger, faster, and serve more clients, the demands placed on their computational components increase and they can become performance bottlenecks. Many of these computational tasks are inherently parallel: they can be run independently for different blocks, files, or I/O requests. this makes them a good fit for GPUs, a class of processor designed specifically for high degrees of parallelism: consumer-grade GPUs have hundreds of cores and are capable of running hundreds of thousands of concurrent threads. However, because the software frameworks built for GPUs have been designed primarily for the long-running, data-intensive workloads seen in graphics or high-performance computing, they are not well-suited to the needs of storage systems. In this paper, we present GPUstore, a framework for integrating GPU computing into storage systems. GPUstore is designed to match the programming models already used these systems. We have prototyped GPUstore in the Linux kernel and demonstrate its use in three storage subsystems: file-level encryption, block-level encryption, and RAID 6 data recovery. Comparing our GPU-accelerated drivers with the mature CPU-based implementations in the Linux kernel, we show performance improvements of up to an order of magnitude. © 2012 ACM.

关键词： Graphics processing unit

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Scalable Distributed Fast Multipole Methods

Scalable Distributed Fast Multipole Methods

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Qi Hu Nail A. Gumerov Ramani Duraiswami University of Maryland Institute for Advanced Computer Studies (UMIACS) USA

the Fast Multipole Method (FMM) allows O(N) evaluation to any arbitrary precision of N-body interactions that arises in many scientific contexts. these methods have been parallelized, with a recent set of papers attempting to parallelize them on heterogeneous CPU/GPU architectures [1]. While impressive performance was reported, the algorithms did not demonstrate complete weak or strong scalability. Further, the algorithms were not demonstrated on nonuniform distributions of particles that arise in practice. In this paper, we develop an efficient scalable version of the FMM that can be scaled well on many heterogeneous nodes for nonuniform data. Key contributions of our work are data structures that allow uniform work distribution over multiple computing nodes, and that minimize the communication cost. these new data structures are computed using a parallel algorithm, and only require a small additional computation overhead. Numerical simulations on a heterogeneous cluster empirically demonstrate the performance of our algorithm.

关键词： Receivers Partitioning algorithms Octrees Graphics processing unit Vegetation Clustering algorithms

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REAL-TIME BLOCK MATCHING MOTION ESTIMATION ONTO GPGPU

REAL-TIME BLOCK MATCHING MOTION ESTIMATION ONTO GPGPU

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IEEE international conference on Image processing

作者： Eduarda Monteiro Marilena Maule Felipe Sampaio Claudio Diniz Bruno Zatt Sergio Bampi Informatics Institute-PPGC-PGMICRO Federal University of Rio Grande do Sul Porto Alegre Brazil

this work presents an efficient method to map Motion Estimation (ME) algorithms onto General Purpose Graphic processing Unit (GPGPU) architectures using CUDA programming model. Our method jointly exploits the massive parallelism available in current GPGPU devices and the parallelization potential of ME algorithms: Full Search (FS) and Diamond Search (DS). Our main goal is to evaluate the feasibility of achieving real-time high-definition video encoding performance running on GPUs. For comparison reasons, multi-core parallel and distributed versions of these algorithms were developed using OpenMP and MPI (Message Passing Interface) libraries, respectively. the CUDA-based solutions achieve the highest speed-up in comparison with OpenMP and MPI versions for both algorithms and, when compared to the state-of-the-art, our FS and DS solutions reach up to 18x and 11x speed-up, respectively.

关键词： Graphics processing units Motion estimation Algorithm design and analysis Computer architecture Real-time systems Diamonds Programming

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An Energy Efficient Multi-Core Modem Architecture for LTE Mobile Terminals

An Energy Efficient Multi-Core Modem Architecture for LTE Mo...

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New Technologies, Mobility and Security (NTMS)

作者： Anas Showk Shadi Traboulsi Attila Bilgic Institute for Integrated Systems University of Bochum Bochum Germany KROHNE Messtechnik GmbH and Company KG Duisburg Germany

Since data rate in wireless communication systems has exponentially increased during the last decade, serious efforts are considered to fulfill their target requirements. therefore, providing a satisfactory hardware to support high data rates while minimizing power consumption is a key design challenge for Long Term Evolution (LTE) mobile terminals. In this paper we introduce an optimized parallel software architecture for LTE mobile terminals using an energy aware scheduling and load balancing. We show that the proposed software architecture on single, dual, triple and quad-core hardware platforms leads to up to 39% energy savings. In addition, different hardware design options are investigated in order to minimize the average power consumption. the homogeneous multi-core with four cores processing the optimized LTE software saves about one quarter of the energy compared to a single-core running at higher clock frequency achieving the same data rate. Considering statistics for the mobile user behavior, the homogeneous multi-core with four cores proves to provide the minimum average power consumption compared to the other hardware architectures considered in this work.

关键词： Hardware Mobile communication Energy consumption Protocols Multicore processing Power demand Instruction sets

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parallel Implementation of Neural Networks Training on Graphic processing Unit

Parallel Implementation of Neural Networks Training on Graph...

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international conference on Biomedical Engineering and Informatics

作者： Yong Liu Yeming Xiao Li Wang Jielin Pan Yonghong Yan The Key Laboratory of Speech Acoustics and Content Understanding Institute of Acoustics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781467311830

Recently artificial neural network (ANN) especially the deep belief network (DBN) becomes more and more popular in the acoustic model training. In order to improve the speed of ANN, the Graphics processing Unit (GPU) is used. this paper gives the training details of the Back-Propagation (BP) neural network acoustic model for speech recognition on GPU, including the parallel reduction application and asynchronous implementation between CPU and GPU. It is 26 times faster than using the single thread Intel~? MKL(Math Kernel Library) implementation.

关键词： GPU BP neural network acoustic model speech recognition

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Real-time processing in dynamic ultrasound elastography: A GPU-based implementation using CUDA

Real-time processing in dynamic ultrasound elastography: A G...

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international Symposium on Signal processing and Its Applications (ISSPA)

作者： Emmanuel Montagnon Sami Hissoiny Philippe Després Guy Cloutier Laboratory of Biorheology and Medical Ultrasonics Université de Montréal Hospital Research Center (CRCHUM) Québec H2L 2W5 Canada Polytechnique Montreal Montreal QC CA Department of Radiation Oncology Université de Montréal Hospital (CHUM) Québec H2L 4M1 Canada

this paper addresses the computational cost of the normalized cross-correlation (NCC) algorithm in ultrasound elastography. parallel implementations of the NCC algorithm based on multicore architectures and a graphical processor unit (GPU) are formulated and applied to radio-frequency (RF) data from dynamic elastography experiments. Compared to single computer processor unit (CPU) performances, results show that parallel implementation of the NCC algorithm allows speedups of less than 5 for multi-threaded execution on CPU and up to 85 using a GPU. processing frame rates from 80 to 173 sec -1 have been achieved for large fields of view with good spatial resolution. the trade-off between accuracy, spatial resolution and computational cost in displacement estimation using the NCC algorithm therefore appears obsolete. Open source codes for implementing the NCC algorithm on GPU are made available at ***.

关键词： Graphics processing unit Ultrasonic imaging Instruction sets Heuristic algorithms Acoustics Computational efficiency Estimation

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An efficient packing algorithm for spatial keyword queries

An efficient packing algorithm for spatial keyword queries

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6th international conference on Convergence and Hybrid Information Technology, ICHIT 2012

作者： Pan, Jinkun Li, Dongsheng Li, Liming National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology 410073 Changsha China Shanghai Garrision 200040 Shanghai China

ISBN: (纸本)9783642326448

With the increase of location-based services, Web contents are being geo-tagged, and spatial keyword queries that retrieve objects satisfying both spatial and keyword conditions are gaining in prevalence. Unfortunately, the state-of-the-art packing algorithms only focus on spatial relationship, and they are not fit for the spatial keyword queries. In this paper, we propose a new packing algorithm named KBS which takes both location and keyword information into consideration, thus optimizing R-tree for spatial keyword queries. Experimental results on both real and synthetic datasets show that our method achieves high performance and space utilization. © 2012 Springer-Verlag.

关键词： Location based services

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Accelerating Boosting-Based Face Detection on GPUs

Accelerating Boosting-Based Face Detection on GPUs

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international conference on parallel processing (ICPP)

作者： David Oro Carles Fern'ndez Carlos Segura Xavier Martorell Javier Hernando Herta Security Barcelona Spain Universitat Politècnica de Catalunya Barcelona Spain

the goal of face detection is to determine the presence of faces in arbitrary images, along with their locations and dimensions. As it happens with any graphics workloads, these algorithms benefit from data-level parallelism. Existing parallelization efforts strictly focus on mapping different divide and conquer strategies into multicore CPUs and GPUs. However, even the most advanced single-chip many-core processors to date are still struggling to effectively handle real-time face detection under high-definition video workloads. To address this challenge, face detection algorithms typically avoid computations by dynamically evaluating a boosted cascade of classifiers. Unfortunately, this technique yields a low ALU occupancy in architectures such as GPUs, which heavily rely on large SIMD widths for maximizing data-level parallelism. In this paper we present several techniques to increase the performance of the cascade evaluation kernel, which is the most resource-intensive part of the face detection pipeline. Particularly, the usage of concurrent kernel execution in combination with cascades generated with the Gentle Boost algorithm solves the problem of GPU underutilization, and achieves a 5X speedup in 1080p videos on average over the fastest known implementations, while slightly improving the accuracy. Finally, we also studied the parallelization of the cascade training process and its scalability under SMP platforms. the proposed parallelization strategy exploits both task and data-level parallelism and achieves a 3.5X speedup over single-threaded implementations.

关键词： Kernel Face detection Graphics processing unit Face parallel processing Instruction sets Training

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A distributed asynchronous and privacy preserving neural network ensemble selection approach for peer-to-peer data mining 12

A distributed asynchronous and privacy preserving neural net...

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5th Balkan conference in Informatics, BCI 2012

作者： Kokkinos, Yiannis Margaritis, Konstantinos G. Department of Applied Informatics Parallel and Distributed Processing Laboratory University of Macedonia P.O. Box 1591 54006 Thessaloniki Greece

ISBN: (纸本)9781450312400

this work describes a fully asynchronous and privacy preserving ensemble selection approach for distributed data mining in peerto- peer applications. the algorithm builds a global ensemble model over large amounts of data distributed over the peers in a network, without moving the data itself, and with little centralized coordination. Only classifiers are transmitted to other peers. Here the test set from one classifier is the train set of the other and vice versa. Regularization Networks are used as ensemble member classifiers. the approach constructs a mapping of all ensemble members to a mutual affinity matrix based on classification rates between them. After the mapping of all members the Affinity Propagation clustering algorithm is used for the selection phase. A classical asynchronous peer-to-peer cycle is continually executed for computing the mutual affinity matrix. the cycle composed of typical grid commands, like send local classifier to a peer k, check for received classifier m in the queue, compute local average positive hits, send results to peer m and send local classifier to a peer k+1. thus the communication model used is simple point-to-point with send-receive commands to or from a single peer. the approach can also be implemented to other types of classifiers. Copyright 2012 ACM.

关键词： Neural networks

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